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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP96002/D, Rev. 2
DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024 words of data RAM (equally divided into X data and Y data memory), 1024 words of fullspeed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA) controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCETM) debug circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units operating in parallel. The DSP96002 has two identical memory expansion ports with control lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which facilitates easy interface with other processors for multiprocessor applications. Linear arrays of DSP96002s can be implemented without glue logic. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The high speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive applications that require floating-point processing and access to large memory subsystems.
Control 18 Control 18
Bus Control
Address Generation Unit (AGU) YAB * XAB * PAB * Program * X Data * Memory Memory 1024 x 32 512 x 32 RAM and RAM 64 x 32 Bootstrap 512 x 32 ROM ROM Instruction Cache DDB YDB XDB PDB GDB Y Data * Memory 512 x 32 RAM 512 x 32 ROM
Bus Control
Address External 32 Address Switch Dual Channel DMA Controller Internal Switch And Bit Manipulation Unit
External Address 32 Address Switch 4 Port B 32 Data AA0306
Port A
4 32-bit Host Interface Timer External Data Bus Switch
32-bit Host Interface Timer External Data Bus Switch
32 Data
Clock Generator
Program Decode Controller
Program Address Generator Program Controller
Program Interrupt Controller
OnCE Data ALU Debug * IEEE Floating Point Controller * 32 x 32 Integer ALU 4 Serial Debug Port
CLK 32-bit Buses * Dual Access (DMA/Core) 1024 x 32 Virtual Locations
MODC/IRQC MODB/IRQB MODA/IRQA RESET
Figure 1 Block Diagram
(c)1996 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 APPENDIX A APPENDIX B
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 BOOTSTRAP CODE FOR DSP96002. . . . . . . . . . . . . . . . . . . . . A-1 X AND Y MEMORY ROM TABLES . . . . . . . . . . . . . . . . . . . . . . . B-1 FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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DSP96002/D, Rev. 2
MOTOROLA
DSP96002 Features
FEATURES
* Digital signal processing core - - - - - - - - - - Efficient 32-bit DSP engine Conforms to IEEE 754-1985 standard for single precision (32-bit) and single extended precision (44-bit) arithmetic Up to 30 Million Instructions Per Second (MIPS) at 60 MHz Parallel operation of Data ALU, Address Generation Unit (AGU), and program controller within the CPU allow more processing per instruction cycle Single-cycle 32 x 32 bit parallel multiplier Highly parallel instruction set with unique DSP addressing modes Nested hardware DO loops Instruction cache extended to operate as 4 K byte (1 K word) Fast auto-return interrupts Address buses: * * * * - One 32-bit unidirectional internal X memory Address Bus (XAB) One 32-bit unidirectional internal Y memory Address Bus (YAB) One 32-bit internal Program Address Bus (PAB) Two 32-bit external address buses
Data buses: * * * * * * One 32-bit bidirectional internal X memory Data Bus (XDB) One 32-bit bidirectional internal Y memory Data Bus (YDB) One 32-bit bidirectional internal Global memory Data Bus (GDB) One 32-bit bidirectional internal DMA Data Bus (DDB) One 32-bit bidirectional internal Program Data Bus (PDB) Two 32-bit external data buses
- *
MCU-like instruction set mnemonics make programming easier On-chip 1024 x 32-bit Program RAM Two independent on-chip 512 x 32-bit data RAMs Two independent on-chip 512 x 32-bit data ROMs (1024 x 32-bit virtual memory) On-chip 64 x 32-bit bootstrap ROM
Memory - - - -
MOTOROLA
DSP96002/DRev. 2
iii
DSP96002 Product Documentation
- - *
Off-chip expansion to 2 x 232 32-bit words of data memory Off-chip expansion to 232 32-bit words of program memory
Miscellaneous features - - Two expansion ports assignable to X data, Y data, or program memory spaces or a combination thereof, effectively doubling off-chip bus bandwidth. Host interface circuitry on each port provides a flexible slave interface to Direct Memory Access (DMA) controllers and external processors for easy design of multimaster systems Write strobe pins support interface to external SRAMs without additional logic Two programmable timers/counters Three external interrupt/mode control lines One external reset line for hardware reset 4-pin OnCE port for unobtrusive, processor speed-independent debugging HCMOS design for operating frequencies from 60 MHz down to DC 223-pin plastic Pin Grid Array (PGA) package or 240-pin Ceramic Quad Flat Pack (CQFP) package 5.0 V power supply
- - - - - - - -
PRODUCT DOCUMENTATION
The two manuals listed in Table 1 are required for a complete description of the DSP96002 and are necessary to design properly with the device. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).
Table 1 Additional Documentation
Document Name DSP96002 User's Manual DSP96002 Data Sheet Description Detailed description of the DSP96002 core processor and peripherals Electrical and timing specifications, and pin and package descriptions Order Number DSP96002UM/AD DSP96002/D
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DSP96002/DRev. 2
MOTOROLA
SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The input and output signals of the DSP96002 are organized into eight functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1. Table 1-1 DSP96002 Functional Signal Groupings
Functional Group Power (VCCN and VCCQ) Ground (GNDN and GNDQ) Clock (CLK) Interrupt and Mode Control Port A (Address, Data, and Control) Port B (Address, Data, and Control) Timer/Event Counters OnCE Port Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-6 Table 1-7 Table 1-8
Figure 1-1 is a diagram of DSP96002 signals by functional group.
MOTOROLA
DSP96002/D, Rev. 2
1-1
Signal/Connection Descriptions Signal Groupings
Power1 VCCN VCCQ Ground2 GNDN GNDQ Clock Input CLK Interrupt and Mode Control MODA/IRQA MODB/IRQB MODC/IRQC RESET
DSP96002
32 / 32 /
Address Bus B BA0-BA31 Data Bus B BD0 - BD31 Port B Bus Control BS1 BS0 BR/W BWR BBS BBL BTT BTS BTA BAE BDE BHS BHA BHR BR BBG BBB BBA
Address Bus A AA0-AA31 Data Bus A AD0-AD31 Port A Bus Control AS1 AS0 AR/W AWR ABS ABL ATT ATS ATA AAE ADE AHS AHA AHR ABR ABG ABB ABA Note: 1. 2.
32 / 32 /
2
Timer/Event Counters TIO0-TIO1
On-Chip Emulation Port (OnCE) DSO DSI/OSO DSCK/OS1 DR
Number of power input pins is package dependent. See Section 3. Number of ground connections is package dependent. See Section
3.
Figure 1-1 Functional Group Pin Allocations
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Power
POWER
Table 1-2 Power Inputs
Power Name VCCN Description Normal Power --VCCN inputs are VCC provided for general use with the DSP96002 peripheral circuits. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Quiet Power--VCCQ inputs provide isolated power for the internal processing logic. The voltage should be well-regulated, and the input should be provided with an extremely low impedance path to the VCC power rail. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
The number of available power connecctions is package-dependent. See Section description of individual package pinouts.
VCCQ
Note:
3 for a detailed
GROUND
Table 1-3 Grounds
Ground Name GNDN Description Normal Ground --GNDP connections provide a ground return for the DSP96002 peripheral circuits. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Quiet Ground --GNDQ is an isolated ground for the internal processing logic. The connection should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
The number of available ground connecctions is package-dependent. See Section description of individual package pinouts.
GNDQ
Note:
3 for a detailed
MOTOROLA
DSP96002/D, Rev. 2
1-3
Signal/Connection Descriptions Clock
CLOCK
Table 1-4 Clock Signal
Signal Name CLK Type Input State During Reset Input Signal Description Clock Input--CLK is a high frequency processor clock input. The frequency is twice the instruction rate. As shown in Figure 1-2, an internal phase generator divides CLK into four phases (t0, t1, t2 and t3), which is the basic instruction execution cycle. Additional tw phases are optionally generated to insert Wait States (WS) into instruction execution. A Wait State is formed by pairing a t2 and tw phase. CLK should be continuous with a 46- 54% duty cycle.
Instruction Cycle t0 CLK No Wait States t1 t2 t3 t0 t1 t2
Instruction Cycle Two Wait States tw t2 tw t2 t3
Figure 1-2 Clock Input and Instruction Cycle Timing
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
Table 1-5 Interrupt and Mode Control
Signal Name RESET Type State During Reset Signal Description Reset--This input is a direct hardware reset of the processor. When RESET is asserted low, the signal is internally synchronized to the input clock (CLK), the DSP is placed in the Reset state, and the internal phase generator is reset. A Schmitt trigger input is used for noise immunity and allows a slowly rising input (such as a capacitor charging) to reliably reset the chip. If RESET is deasserted synchronous to the input clock (CLK), exact start-up timing is guaranteed, allowing multiple processors to start-up synchronously and operate together in "lock-step." When the RESET pin is deasserted, the initial chip operating mode is latched from the MODA, MODB and MODC pins. Mode Select A/External Interrupt Request A--This input is internally synchronized to the input clock (CLK). MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB and MODC select one of eight initial chip operating modes latched into the Operating Mode Register (OMR) when the RESET pin is deasserted. If IRQA is asserted synchronous to the input clock (CLK), multiple processors can be resynchronized by using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop standby state and IRQA is asserted, the processor will exit the Stop state. Mode Select B/External Interrupt Request B--This input is internally synchronized to the input clock (CLK). MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB and MODC select one of eight initial chip operating modes latched into the Operating Mode Register (OMR) when the RESET pin is deasserted. If IRQB is asserted synchronous to the input clock (CLK), multiple processors can be resynchronized by using the WAIT instruction and asserting IRQB to exit the Wait state.
Input Input
MODA/IRQA
Input Input
MODB/ IRQB
Input Input
MOTOROLA
DSP96002/D, Rev. 2
1-5
Signal/Connection Descriptions Port A and Port B
Table 1-5 Interrupt and Mode Control (Continued)
Signal Name MODC/IRQC Type State During Reset Signal Description Mode Select C/External Interrupt Request C--This input is internally synchronized to the input clock (CLK). MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB and MODC select one of eight initial chip operating modes latched into the Operating Mode Register (OMR) when the RESET pin is deasserted. If IRQC is asserted synchronous to the input clock (CLK), multiple processors can be resynchronized by using the WAIT instruction and asserting IRQC to exit the Wait state.
Input Input
PORT A AND PORT B
Port A and Port B are identical in pinout and function. The following pin descriptions apply to both ports. Each port may be a bus master and each port has a slave Host Interface which can be accessed on demand.
Table 1-6 Port A and Port B
Signal Name
AA0-AA31 BA0-BA31
Type
Input or Output
State During Reset
Tri-stated
Signal Description
Address Bus--A0-A31 specify the address for external program and data memory accesses. If there is no external bus activity, A0-A31 remain at their previous values. The Address Enable (AE) input acts as an output enable control for A0-A31. A0-A31 are stable whenever the transfer strobe TS is asserted and may change only when TS is deasserted. The signal direction depends on whether the DSP is the bus master: * Bus Master--A0-A31 are tri-state, active high outputs. * Not a Bus Master--A2-A5 are active high inputs used to select the Host Interface register. Lines A0- A1 and A6-A31 are tri-stated. As inputs, A2-A5 may change asynchronously relative to the input clock (CLK).
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
AD0-AD31 BD0-BD31
Type
Input/ Output
State During Reset
Tri-stated
Signal Description
Data Bus--D0-D31 are tri-state, active high, bidirectional input/outputs whether the DSP is a bus master or not. The Data Enable (DE) input acts as an output enable control for D0-D31. As a bus master, the data lines are controlled by the CPU instruction execution or the DMA controller. D0- D31 are also the Host Interface data lines. If there is no external bus activity, D0-D31 are tri-stated. Space Select--These signals can be viewed in different ways, depending on how the external memories are mapped. They support splitting memory spaces among ports, and mapping multiple memory spaces into the same physical memory locations. S0 and S1 are outputs when the DSP is the bus master and tri-stated when the DSP is not a bus master. Timing is the same as the address lines A0- A31. Read/Write--R/W is a an output when the DSP is the bus master and an input when not a bus master. Bus master timing is the same as the DSP96002 address lines, giving an "early write" signal for DRAM interfacing. R/W is high for a read access and low for a write access. The R/W pin is also the Host Interface read/write input. As an input, R/W may change asynchronously relative to the input clock. R/W goes high if the external bus is not used during an instruction cycle. Write Strobe --WR is an output when the DSP is the bus master and tri-stated when it is not a bus master. WR supports a glueless interface to external SRAMs. WR is asserted during external memory write cycles to indicate that the address lines A0-A32, S1, S0, BS, BL, and R/W are stable. The output data goes to the data bus after WR is asserted. WR requires a weak external pull-up resistor and can be connected directly to the WE pin of a Static RAM. Bus Strobe--BS is an output when the DSP is the bus master and tri-stated when it is not a bus master. Bus strobe is asserted at the start of a bus cycle (providing an "early bus start" signal for DRAM interfacing) and deasserted at the end of the bus cycle. The early negation provides an "early bus end" signal useful for external bus control. If the external bus is not used during an instruction cycle, BS remains deasserted until the next external bus cycle.
AS0-AS1 BS0-BS1
Output
Tri-stated
AR/W BR/W
Input or Output
Tri-stated
AWR BWR
Output
Tri-stated
ABS BBS
Output
Tri-stated
MOTOROLA
DSP96002/D, Rev. 2
1-7
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ATT BTT
Type
Output
State During Reset
Tri-stated
Signal Description
Transfer Type--TT is an output when the DSP is the bus master and tri-stated when it is not a bus master. When the DSP is the bus master, TT is controlled by an on-chip page circuit. TT is asserted when a fast access memory mode (Page, Static Column, Nibble or Serial Shift Register) is detected. If the external bus is not used during an instruction cycle, or a fault is detected by the page circuit during an external access, TT remains deasserted. The parameters of the page circuit fault detection are user programmable. Transfer Strobe--TS is an output when the DSP is the bus master and an input when it is not a bus master. When the DSP is the bus master, TS is asserted to indicate that the address lines A0-A31, S1, S0, BS, BL and R/W are stable and that a bus read or bus write transfer is taking place. During a read cycle, input data is latched inside the DSP96002 on the rising edge of TS. During a write cycle, output data is placed on the data bus after TS is asserted. Therefore, TS can be used as an output enable control for external data bus buffers if they are present. If the external bus is not used during an instruction cycle, TS remains deasserted until the next external bus cycle. An external flip-flop can delay TS, if required, for slow devices or more address decoding time. The TS pin is also the Host Interface transfer strobe input used to enable the data bus output drivers during host read operations and to latch data inside the Host Interface during host write operations. As an input, TS may change asynchronously relative to the input clock. Write data is latched inside the Host Interface on the rising edge of TS. When the DSP is the bus master, the combination of BS and TS can be decoded externally to determine the status of the current bus cycle and to generate hardware strobes useful for latching address and data signals.
ATS BTS
Input or Output
Tri-stated
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ATA BTA
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Transfer Acknowledge-- The TA input is a synchronous "DTACK" function that can extend an external bus cycle indefinitely. TA must be asserted and deasserted synchronously to the input clock (CLK) for proper operation. TA is sampled on the falling edge of the input clock (CLK). Any number of wait states (0, 1, 2, ..., infinity) may be inserted by keeping TA deasserted. In a typical operation, TA is first deasserted at the start of a bus cycle, then is asserted to enable completion of the bus cycle, and finally is deasserted before the next bus cycle.The current bus cycle completes one clock period after TA is asserted synchronously to CLK. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. If TA is tied low (asserted) and no wait states are specified in the BCR, zero wait states will be inserted into external bus cycles.
Note: If the DSP96002 is the bus master and there is no external bus activity or the DSP96002 is not the bus master, then the TA input is ignored by the core.
AAE BAE
Input
Input, ignored during reset
Address Enable--AE is an input that must be asserted and deasserted synchronous to the input clock (CLK) for proper operation. If the DSP is the bus master, AE is asserted to enable the A0-A31 address output drivers. If AE is deasserted, the address output drivers are tri-stated. If the DSP is not a bus master, the address output drivers are tristated regardless of whether AE is asserted or deasserted. The function of AE is to allow implementation of multiplexed bus systems. An example of such an implementation is a multiplexed address1/address2 bus used with dual port memories, such as dynamic VRAMs.
Note: There must be at least one undriven CLK period between enables for multiplexed buses to allow one bus to tristate before another bus is enabled. External control is responsible for this timing. For non-multiplexed systems, AE should be tied low.
MOTOROLA
DSP96002/D, Rev. 2
1-9
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ADE BDE
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Data Enable--DE is an input that must be asserted and deasserted synchronous to the input clock (CLK) for proper operation. If a bus master or the Host Interface is being read, DE is asserted to enable the D0-D31 data bus output drivers. If DE is deasserted, the data bus output drivers are tri-stated. If not a bus master, the data bus output drivers are tri-stated regardless of whether DE is asserted or deasserted. Read-only bus cycles may be performed even though DE is deasserted. The function of DE is to allow multiplexed bus systems to be implemented. An example is a multiplexed data1/data2 bus used for long word transfers with one 32-bit wide memory.
Note: There must be at least one undriven CLK period between enables for multiplexed buses to allow one bus to tristate before another bus is enabled. External control is responsible for this timing. For non-multiplexed systems, DE should be asserted (tied low).
AHS BHS
Input
Input
Host Select--HS is an input that may change asynchronous to the input clock. HS is asserted low to enable selection of the Host Interface functions by the address lines A2-A5. If TS is asserted when HS is asserted, a data transfer with the Host Interface will take place.
Note: Both HS and HA must be tied high to disable the Host Interface. When HA is asserted, HS is ignored.
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
AHA BHA
Type
Input
State During Reset
Input
Signal Description
Host Acknowledge--HA is an input that may change asynchronously to the input clock. HA is used to acknowledge either an interrupt request or a DMA request by the Host Interface. When the Host Interface is not in DMA mode, asserting TS when HA and HR are asserted will enable the contents of the Host Interface Interrupt Vector Register (IVR) onto the data bus outputs D0-D31. This provides an interrupt acknowledge capability compatible with MC68000 family processors. If the Host Interface is in DMA mode, HA is used as a DMA transfer acknowledge input and it is asserted by an external device to transfer data between the Host Interface registers and an external device. In DMA read mode, HA is asserted to read the Host Interface RX register on the data bus outputs D0-D31. In DMA Write mode, HA is asserted to strobe external data into the Host Interface TX register. Write data is latched into the TX register on the rising edge of HA.
AHR BHR
Output
Driven high
Host Request--HR is an output that is never tri-stated. The host request HR is asserted to indicate that the Host Interface is requesting service--either an interrupt request or a DMA request--from an external device. The HR output may be connected to interrupt request input IRQA, IRQB, or IRQC of another DSP96002. The on-chip DMA Controller channel of the other DSP96002 can select the interrupt request input as a DMA transfer request input. Bus Request--BR is an output that is never tri-stated. BR is asserted when the CPU or DMA is requesting bus mastership. BR is deasserted when the CPU or DMA no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP96002 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP96002 is the bus master (see the description of bus "parking" in the BA pin description). The RH bit in the Bus Control Register allows BR to be asserted under software control even though the CPU or DMA does not need the bus. BR is typically sent to an external bus arbitrator, which controls the priority, parking, and tenure of each DSP96002 on the same external bus. BR is only affected by CPU or DMA requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the Bus Slave state.
ABR BBR
Output
Driven high
MOTOROLA
DSP96002/D, Rev. 2
1-11
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ABG BBG
Type
Input
State During Reset
Input, ignored during reset
Signal Description
Bus Grant--BG is an input that must be asserted/ deasserted synchronous to the input clock (CLK) for proper operation. BG is asserted by an external bus arbitration circuit indicating the DSP96002 has become the pending bus master. When BG is asserted, the DSP96002 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction, which requires more than one external bus cycle for execution.
Note: Indivisible read-modify-write instructions (BSET, BCLR, BCHG) will not give up bus mastership until the end of the current instruction. BG is ignored during hardware reset.
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ABA BBA
Type
Output
State During Reset
Tri-stated
Signal Description
Bus Acknowledge--BA is an open drain output. When deasserting BA, the DSP96002 drives BA high during half a CLK cycle and then disables the active pull-up. In this way, only a weak external pull-up resistor is required to hold the line high. BA may be directly connected to BB in order to obtain the same functionality as the MC68040 BB pin. When BG is asserted, the DSP96002 becomes the pending bus master. It waits until BB is negated by the previous bus master, indicating that the previous bus master is off the bus. The pending bus master asserts BA to become the current bus master. BA is asserted when either the CPU or the DMA has taken the bus and is the bus master. While BA is asserted, the DSP96002 is the owner of the bus (the bus master). When BA is deasserted, the DSP96002 is a bus slave. BA may be used as a tri-state enable control for external address, data, and bus control signal buffers.
Note: A current bus master may keep BA asserted after ceasing bus activity, regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to use the bus repeatedly without rearbitration until some other device wants the bus.
The current bus master keeps BA asserted during indivisible read-modify-write bus cycles, regardless of whether BG has been deasserted by the external bus arbitration unit. This form of "bus locking" allows the current bus master to perform atomic operations on shared variables in multitasking and multiprocessor systems. Current instructions that perform indivisible read-modifywrite bus cycles are BCLR, BCHG and BSET.
MOTOROLA
DSP96002/D, Rev. 2
1-13
Signal/Connection Descriptions Port A and Port B
Table 1-6 Port A and Port B (Continued)
Signal Name
ABB BBB
Type
Input
State During Reset
Input
Signal Description
Bus Busy--BB is an input that must be asserted and deasserted synchronous to the input clock (CLK) for proper operation. BB is deasserted when there is no bus master on the external bus. In multiple DSP96002 systems, all BB inputs are tied together and are driven by the logical AND of all BA outputs. BB is asserted when a pending bus master becomes the current bus master (directly or indirectly by BA assertion). BB is deasserted by the current bus master (directly or indirectly by BA deassertion) to indicate that it is off the bus and is no longer the bus master. The pending bus master monitors the BB signal until it is deasserted. Then the pending bus master asserts BA to become the current bus master, which asserts BB directly or indirectly.
Note: Use of pull-up resistors is recommended.
ABL BBL
Output
Driven high
Bus Lock--BL is an output that is never tri-stated. Asserted at the start of an external indivisible Read-Modify-Write (RMW) bus cycle (providing an "early bus start" signal for DRAM interfacing) and deasserted at the end of the write bus cycle, BL remains asserted between the read and write bus cycles of the read-modify-write bus sequence. BL can be used to indicate that special memory timing (such as RMW timing for DRAMs) may be used or to "resource lock" an external multi-port memory for secure semaphore updates. The early negation provides an "early bus end" signal useful for external bus control. If the external bus is not used during an instruction cycle, BL remains deasserted until the next external indivisible read-modify-write bus cycle. BL also remains deasserted if the external bus cycle is not an indivisible read-modify-write bus cycle or if there is an internal RMW bus cycle. The only instructions that automatically assert BL are a BSET, BCLR or BCHG instruction, which accesses external memory. BL can also be asserted by setting the LH bit in the BCR.
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DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions Timer/Event Counter
TIMER/EVENT COUNTER
Table 1-7 Timer/Event Counters
Signal Name
TIO0- TIO1
Type
Input or Output
State During Reset
Input
Signal Description
Timer/Event Counter --The bidirectional TIO signal connects to the on-chip Timer/Event Counter. When TIO is used as an input, the module is functioning as an external event counter or is measuring external pulse width/signal period. When TIO is used as an output, the module is functioning as a timer, and TIO becomes the timer pulse. When the TIO pin is not used by the timer module, it can be used as a General Purpose Input/Output (GPIO) pin. The timer can use internal or external clocking and can interrupt the processor after a number of events specified by a user program, or it can signal an external device after counting internal events. The timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurs. When the timer is disabled, the TIO pin becomes tri-stated. To prevent undesired spikes from occurring, the TIO pin should be pulled up or down when it is not in use.
MOTOROLA
DSP96002/D, Rev. 2
1-15
Signal/Connection Descriptions OnCE Port
OnCE PORT
Table 1-8 On-Chip Emulation Port (OnCE) Signals
Signal Name DSI/OS0 Signal Type Output State during Reset Low Output Signal Description
Debug Serial Input/Chip Status 0--Serial data or commands are provided to the OnCE controller through the DSI/OS0 signal when it is an input. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data is latched on the falling edge of the DSCK serial clock. Data is always shifted into the OnCE serial port Most Significant Bit (MSB) first. When the DSI/OS0 signal is an output, it works in conjunction with the OS1 signal to provide chip status information. The DSI/OS0 signal is an output when the processor is not in Debug mode. When switching from output to input, the signal is tri-stated.
Note: If the OnCE interface is in use, an external pull-down resistor should be attached to this pin. If the OnCE interface is not in use, the resistor is not required.
DSCK/ OS1
Output
Low Output
Debug Serial Clock/Chip Status 1--The DSCK/OS1 signal supplies the serial clock to the OnCE when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. When switching from input to output, the signal is tri-stated. When it is an output, this signal works with the OS0 signal to provide information about the chip status. The DSCK/OS1 signal is an output when the chip is not in Debug mode.
Note: If the OnCE interface is in use, an external pull-down resistor should be attached to this pin. If the OnCE interface is not in use, the resistor is not required.
1-16
DSP96002/D, Rev. 2
MOTOROLA
Signal/Connection Descriptions OnCE Port
Table 1-8 On-Chip Emulation Port (OnCE) Signals (Continued)
Signal Name DSO Signal Type Output State during Reset Output, pulled high Signal Description
Debug Serial Output--Data contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port MSB first. Data is clocked out of the OnCE serial port on the rising edge of DSCK. The DSO signal also provides acknowledge pulses to the external command controller. When the chip enters the Debug mode, the DSO signal will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After the OnCE receives a read command, the DSO signal will be pulsed low to indicate that the requested data is available and the OnCE serial port is ready to receive clocks in order to deliver the data. After the OnCE receives a write command, the DSO signal will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.
DR
Input
Input
Debug Request--The Debug Request input (DR) allows the user to enter the Debug mode of operation from the external command controller. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the DSI line. While in Debug mode, the DR signal lets the user reset the OnCE controller by asserting it and deasserting it after receiving acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. DR must be deasserted after the OnCE responds with an acknowledge on the DSO signal and before sending the first OnCE command. Asserting DR will cause the chip to exit the Stop or Wait state. Having DR asserted during the deassertion of RESET will cause the DSP to enter Debug mode.
Note: If the OnCE interface is not in use, attach an external pull-up resistor to the DR input.
MOTOROLA
DSP96002/D, Rev. 2
1-17
Signal/Connection Descriptions OnCE Port
1-18
DSP96002/D, Rev. 2
MOTOROLA
SECTION 2 SPECIFICATIONS
INTRODUCTION
The digital signal processor (DSP) is fabricated using high-density Complementary Metal Oxide Semiconductor (CMOS) with Transistor-TransistorLogic (TTL) compatible inputs and outputs. This section covers the maximum ratings, thermal characteristics, and electrical characteristics of the DSP96002. Note: Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
MOTOROLA
DSP96002/D, Rev. 2
2-1
Specifications Thermal Characteristics
Table 2-1 Maximum Electrical Ratings
Rating
Supply Voltage All Input Voltages Current Drain per Pin excluding VCC and VSS1 Operating Temperature Range Storage Temperature
Note: GND = 0 VDC
Symbol
VCC Vin I TJ Tstg
Value
-0.3 to +7.0 GND - 0.5 to VCC + 0.5 10 -40 to +100 -55 to +150
Unit
V V mA C C
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic
Junction to Ambient1 Junction to Case2 Thermal characterization parameter
Note: 1.
Symbol
RJA or JA RJC or JC
PGA Value
22 5.7 5.2
CQFP Value
31 1.6 1.0
Unit C/W C/W C/W
JT
2.
Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature.
2-2
DSP96002/D, Rev. 2
MOTOROLA
Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristic1
Supply Voltage, +10% at 33.3 MHz +5% at 40 MHz +5% at 60 MHz Except CLK, RESET MODA, MODB,MODC Except CLK, MODA, MODB, MODC CLK CLK RESET MODA, MODB, MODC MODA, MODB, MODC -- @2.4 V/0.5 V
Symbol
VCC
Min
4.5 4.75 4.75 2.0
Typical
5.0 5.0 5.0 --
Max
5.5 5.25 5.25 VCC
Unit
V V V V
Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input High Voltage Input Low Voltage Input Leakage Current Tri-State (OffState) Input Current Output High Voltage Output High Voltage Output Low Voltage
VIH
VIL
-0.5
--
0.8
V
VIHC VILC VIHR VIHM VILM Iin
4.0 -0.5 2.5 3.5 -0.5 -10
-- -- -- -- -- --
VCC 0.6 VCC VCC 2.0 10
V V V V V A
ITSI IOH = -10 A IOH = -0.4 mA IOL = 10 A
-10 VCC - 0.1 2.4 --
--
10
A
VOHC VOH VOLC
-- -- --
-- -- 0.1
V V V
MOTOROLA
DSP96002/D, Rev. 2
2-3
Specifications DC Electrical Characteristics
Table 2-3 DC Electrical Characteristics (Continued)
Characteristic1
Output Low Voltage Power Dissipation Total Supply Current IOL = 3.2 mA f = 33.3 MHz2,3 f = 40 MHz2,3 f = 60 MHz2,3 5 V, 33.3 MHz Wait Mode2,3 Stop Mode2,3 5 V, 40 MHz Wait Mode2,3 Stop Mode2,3 5 V, 60 MHz Wait Mode2,3 Stop Mode2,3 Input Capacitance4
Note: 1.
Symbol
VOL
Min
-- -- -- -- -- -- -- -- -- -- -- -- -- --
Typical
-- 1.0 1.25 1.75 200 18 80 250 20 100 350 22 300 10
Max
0.4 -- -- -- 350 26 400 400 34 500 500 40 600 --
Unit
V
PD IDD IDDW IDDS IDD IDDW IDDS IDD IDDW IDDS Cin
W mA mA A mA mA A mA mA A pF
--
2. 3. 4.
DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C PD is measured for VIL 0.2 V, VIH VCC - 0.2V. with no DC loads. CLK is driven by a 50% dutycycle oscillator. In order to obtain these results all inputs must be terminated (i.e., not allowed to float). Input capacitance is not tested in production.
2-4
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms shown in this section are tested with the following values:
VIL maximum of 0.5 V VIH minimum of 2.4 V for all pins1
Note: 1. CLK, RESET, MODA, MODB, and MODC are tested using the input levels described in DC Electrical Characteristics on page 2-3.
AC timing specifications that are referenced to a device input signal are measured in production with respect to the VIH/VIL levels of the respective input signal's transition. AC timing specifications that are referenced to a device's output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. For load capacitances greater than 50pF, the drive capability of the output pins derates linearly at 1.5 ns per 20 pF of additional capacitance from 50 pF to 200 pF of loading, and at 2 ns per 20 pF of additional capacitance for loads greater than 200 pF.
Pulse Width Low VIH Input Signal midpoint1 Fall Time Note: 1. VIL Rise Time 90% 50% 10% High
The midpoint is VIL + (VIH - VIL)/2
Figure 2-1 Signal Measurement Reference
MOTOROLA
DSP96002/D, Rev. 2
2-5
Specifications AC Electrical Characteristics
Clock Operation
The DSP96002 system clock is derived from a crystal or an external system clock signal. The clock input is an active high input, high frequency processor clock. The frequency is twice the instruction rate. An internal phase generator divides CLK into four phases (t0, t1, t2 and t3), which is the basic instruction execution cycle. Additional tw phases are optionally generated to insert Wait States (WS) into instruction execution. A wait state is formed by pairing a t2 and tw phase. CLK should be continuous with a 46-54% duty cycle. Table 2-4 Clock Operation
No.
1
Characteristic
2
Symb.
33.3 MHz3
40 MHz4
60 MHz4
Unit
Min Max Min Max Min Max
Instruction Cycle Time = 2TC = 4T Instruction Cycle Time = 2TC = 4T Wait State = TC = 2T Wait State = TC = 2T 71 72 73 74a 74b
Note:
Icyc WS Tc
60 30 30 -- --
-- -- -- 4 4 16 16
50 25 25 -- -- 11.5 11.5
-- -- -- 4 4 13.5 13.5
33.3 16.7 16.7 -- -- 7.7 7.7
-- -- -- 4 4 9.5 9.5
ns ns ns ns ns ns ns
CLK Cycle Time CLK Cycle Time CLK Rise Time CLK Fall Time CLK High CLK Low
1. 2.
Th Tl
14 14
3. 4.
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C 46%-54% Duty Cycle 46.7%-53.3% Duty Cycle
Th
CLK
Tl
74a 71 74b 73
VIHC Midpoint1 VILC
72
Note:
1.
The midpoint is 0.5 (VCC - GND).
Figure 2-2 CLK Timing Diagram
2-6
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
Arbitration Bus Timing
Table 2-5 Arbitration Bus Timing
33.3 MHz No.
1
40 MHz
Characteristic
2
60 MHz Unit
Min Max Min Max Min Max
1 2 3 4 5 6 7 8 9 9a
Note:
CLK High to BR Asserted / Deasserted BG Valid to CLK High (Setup) CLK High to BG Invalid (Hold) CLK High to BA Asserted / Deasserted BB Valid to CLK High (Setup) CLK High to BB Invalid (Hold) CLK High to A0-A31, S0-S1, R/W, BS, TT, and BL Active A0-A31, S0-S1, R/W, BS, and TT tristate to BA Deasserted CLK High to A0-A31, S0-S1, R/W, BS, and TS tri-state CLK Low to BA tri-state
1. 2.
2 6 2 2 6 2 2 0 2 2
14 -- -- 14 -- -- 10 -- 12 12
2 5 2 2 5 2 2 0 2 2
12 -- -- 12 -- -- 8 -- 10 10
2 5 2 2 4 2 2 0 2 2
10 -- -- 10 -- -- 7 -- 8 8
ns ns ns ns ns ns ns ns ns ns
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C
MOTOROLA
DSP96002/D, Rev. 2
2-7
Specifications AC Electrical Characteristics
CLK (input) 1 BR (output) 2 BG (input) 3
BB (input) 5 6 BA (output) A0-A31, R/W, S0-S1, BS, TT, BL (output) TS (output) WR write cycle (Tri-state)
4 7
(Tri-state) 31
(Tri-state) 41
Figure 2-3 Bus Acquisition Timing
2-8
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
CLK (input) 1 BR (output) 2 BG (input) 3 BA (output) 8 A0-A31, R/W, S0-S1 (output) BS (output) 43 TS (output) 9 42 43a WR write cycle 42a 9 (Tri-state) (Tri-state) (Tri-state) 39 9 4 9a (Tri-state)
9
(Tri-state)
Figure 2-4 Bus Release Timing
MOTOROLA
DSP96002/D, Rev. 2
2-9
Specifications AC Electrical Characteristics
External Bus Relative Timing
Table 2-6 External Bus Relative Timing
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
10 A0-A31, S0-S1, R/W Valid to TS Asserted Expression: A0-A31, S0-S1, R/W Valid to TS Deasserted TS Width Asserted WR Width Asserted TS Deasserted to R/W, A0-A31 Invalid WR Deasserted to R/W, A0-A31 Invalid TS Width Deasserted WR Width Deasserted TS Asserted to D0-D31 Valid (Write Cycle) D0-D31 Valid to TS Deasserted (Write Cycle) D0-D31 Valid to WR Deasserted (Write Cycle) TS Deasserted to D0-D31 Invalid (Write Cycle) WR Deasserted to D0-D31 Invalid (Write Cycle) TS Asserted to D0-D31 Active (Write Cycle) TS Deasserted to D0-D31 Tri-state (Write Cycle) 105 166 7.55 13.56 4.05 9.56 ns
11 12 12a 13 13a 14 14a 15 16 16a 17 17a 18 19
427 309 2727 610 6 2112 18 -- 1215 1228 610 6 1017 --
-- -- -- -- -- -- -- 2014 -- -- -- -- -- 1619
33.58 259 2227 6.511 3.5 1813 15 -- 8.516 1029 6.511 3.5 1018 --
-- -- -- -- -- -- -- 17.514 -- -- -- -- -- 13.519
25.08 179 1527 6.511 2.5 1613 10 -- 616 6.529 6.511 2.5 7.718 --
-- -- -- -- -- -- -- 1514 -- -- -- -- -- 1119
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2-10
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
Table 2-6 External Bus Relative Timing (Continued)
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
19a 20 21 22 23 WR Deasserted to D0-D31 Three-state (Write Cycle) TS Deasserted to D0-D31 Active (Write Cycle) TS Asserted to D0-D31 Valid (Read Cycle) TS Deasserted to D0-D31 Invalid (Hold) (Read Cycle) A0-A31, S0-S1, R/W Valid to D0-D31 Valid (Read Cycle)24 -- 3520 -- 0 -- 1619 -- 2122 -- 3225 -- 31.521 -- 0 -- 13.519 -- 17.523 -- 26.526 -- 26.521 -- 0 -- 1119 -- 1423 -- 2126 ns ns ns ns ns
Note:
1. 2.
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND= 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% and no wait states Assuming duty cycle in the range 46%-54% and no wait states Th-4 Th (WS + 1)Tc + Th-2 (WS + 1)Tc + Th - 3 (WS + 1)Tc Tl - 8 Tl - 5 Tc - 9 13. 14. 15. 16. 17. 18. 19. 20. 21. Tc - 7 Tl + 4 (WS)Tc + Th - 2 (WS)Tc + Th - 3 Tl - 4 Tl - 1.5 Tl Tc + Tl - 9 Tc + Tl - 5 22. 23. 24. 25. 26. 27. 28. 29. (WS + 1)Tc - 9 (WS + 1)Tc - 7.5 Using Th minimum (WS + 1)Tc + Th - 12 (WS + 1)Tc + Th - 10 Tc - 3 Th - 2 Th - 1.5
3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
MOTOROLA
DSP96002/D, Rev. 2
2-11
Specifications AC Electrical Characteristics
A0-A31, S0-S1 (output) (see note) R/W (output) 10 TS (output) 15 D0-D31 (Tri-state) 18 20 14a WR
11
23
10 13 12 19 16 DATA OUT 17 (Tri-state) 21 DATA IN 22 (Tri-state) 14 13
17a 16a
19a 10 11 Note: During Read-Modify-Write instructions, A0-A31, S0-S1 do not change. 12a 13a
Figure 2-5 External Bus Relative Timing
2-12
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
External Bus Synchronous Timing
Table 2-7 External Bus Synchronous Timing
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
31 32 33 34 35 36 37 38 39 40 41 41a 42 42a 43 43a 44 44a CLK High to A0-A31, S0-S1, R/W Valid and TT, BS, BL Asserted CLK High to A0-A31, S0-S1, R/W Invalid CLK High to D0-D31 Valid (Write Cycle) CLK High to D0-D31 Invalid (Write Cycle) CLK High to D0-D31 Active (Write Cycle) CLK High to D0-D31 Three-state (Write Cycle) D0-D31 Valid to CLK Low (Setup) (Read Cycle) CLK Low to D0-D31 Invalid (Hold) (Read Cycle) CLK High to TT, BS, BL Deasserted BS, TT Width Deasserted CLK Low to TS Asserted CLK High TS tri-state TS Hold Time from CLK Low WR Hold Time from CLK Low CLK Low to TS Deasserted CLK Low to WR Deasserted TS Deasserted to BS Asserted (Two Successive Bus Cycles) WR Deasserted to BS Asserted (Two Successive Bus Cycles) 2 2 2 2 2 -- 0 11 2 256 2 2 2 1.5 -- -- 78 -- 14 -- 14 -- -- 12 -- -- 14 -- 11 11 -- -- 16 19 -- 6 2 1.5 2 1.5 1.5 -- 0 9 2 217 1.5 1.5 1.5 1.5 -- -- 6.59 -- 12 -- 12 -- -- 10 -- -- 12 -- 9.5 9.5 -- -- 13 16 -- 3.5 2 1.5 2 1.5 1.5 -- 0 7 2 16.57 1.5 1.5 1.0 1.0 -- -- 6.59 -- 10 -- 10 -- -- 8.5 -- -- 10 -- 8 8 -- -- 9 13 -- 3. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MOTOROLA
DSP96002/D, Rev. 2
2-13
Specifications AC Electrical Characteristics
Table 2-7 External Bus Synchronous Timing (Continued)
No.
45 46 47
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
BS Asserted to TA Asserted5. TA Valid to CLK High (Setup)5. CLK High to TA Invalid (Hold)
1. 2.
-- 3 8
1510 -- --
-- 3 7
12.511 -- --
-- 3 6
9.511 -- --
ns ns ns
Note:
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C 3. Assuming duty cycle in the range 46.7%-53.3% and no wait states 4. Assuming duty cycle in the range 46%-54% and no wait states 5. Timing 45 or timing 46 should be satisfied. 6. Tc-5 7. Tc-4 8. Tl-7 9. Tl-5 10. Tc-15 11. Tc-12.5
2-14
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
CLK (input) 31 A0-A31, R/W, S0-S1 (output) 32
39
40
BS, TT (output) 41 43 TS (output) 45 WR (output) 41a 42 47 43a 44a 44
42a TA (input) 46 33 D0-D31 (output) 37 35 D0-D31 (input) 38 36 34
Figure 2-6 External Bus Synchronous Timing--No Wait States
MOTOROLA
DSP96002/D, Rev. 2
2-15
Specifications AC Electrical Characteristics
CLK (input) 31 A0-A31, R/W, S0-S1, (output) 32
39 40
BS, TT (output) 44 41 43 TS (output) 41a WR (output) 42a 43a 44a
46 TA (input) 47
46
42
47
Figure 2-7 External Bus Synchronous Timing--One Wait State
2-16
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
CLK (input) 31 A0-A31, S0-S1 (output) 32
R/W (output) 39 31 BS, TT (output) 41 TS (output) 31 WR (output) 41a BL (output) 39 42 39 44a 43a 44 43 40 39
42a
Figure 2-8 Read-Modify-Write Cycle Timing--No Wait States
MOTOROLA
DSP96002/D, Rev. 2
2-17
Specifications AC Electrical Characteristics
Multiplexed Bus Timing
Table 2-8 Multiplexed Bus Timing
No.
51 52 53 54 55 56 57 61 62 63 64 65 66
1
Characteristic
AE Asserted to CLK Low5
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
8 2 2 2 0 1 2 8 14 2 2 0 1 146 14 12 -- 128 -- -- 146 2 12 -- 128 -- 6.5 2 2 2 0 1 1.5 6.5 2 2 2 0 1 11.56 12 10 -- 9.59 -- -- 11.56 12 10 -- 9.59 -- 5.5 2 1.5 1.5 0 1 1.5 5.5 2 1.5 1.5 0 1 96 10 8 -- 79 -- -- 96 10 8 -- 79 -- ns ns ns ns ns ns ns ns ns ns ns ns ns
AE Asserted to A0-A31 Valid AE Deasserted to A0-A31 tri-state AE Deasserted to A0-A31 Invalid AE Asserted to CLK High7 AE Asserted to A0-A31 Active CLK High to A0-A31 Active DE Asserted to CLK Low5, 10 DE Asserted to D0-D31 Valid DE Deasserted to D0-D31 Tri-state DE Deasserted to D0-D31 Invalid DE Asserted to CLK High7, 10 DE Asserted to D0-D31 Active
1. 2.
Note:
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% Assuming duty cycle in the range 46%-54% Th minimum Th Tl minimum Tl-4 Tl-2 For Host Interface data output, only timings 62, 63, 64, and 66 apply.
3. 4. 5. 6. 7. 8. 9. 10.
2-18
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
CLK (input) 51 AE (input) 52 56 A0-A31 (output) 53 54 53 31 57 54 55
Figure 2-9 Address Bus Enable/Disable Timing
CLK (input) 61 DE (input) 62 66 D0-D31 (output) 63 33 64 35 64 63 65
Figure 2-10 Data Bus Enable/Disable Timing
MOTOROLA
DSP96002/D, Rev. 2
2-19
Specifications AC Electrical Characteristics
Host Timing
Table 2-9 Host Timing
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
101 102 103 104 105 106 A2-A5, R/W Valid to TS Asserted (Setup) TS Deasserted to A2-A5, R/W Invalid (Hold) TS Asserted to D0-D31 Out Valid TS Asserted to D0-D31 Out Valid5 TS, HA Deasserted to D0-D31 Out Invalid (Hold) TS, HA Asserted to D0-D31 Out Active TS, HA Deasserted to D0-D31 Tri-state A2-A5, R/W Valid to D0-D31 Valid to D0-D31 Out Valid A2-A5, R/W Valid to D0-D31 Valid to D0-D31 Out Valid5 HS, HA Asserted to D0-D31 Out Valid (Access Time) HS, HA Asserted to D0-D31 Out Valid5 D0-D31 In Valid to TS, HA Deasserted (Setup) TS, HA Deasserted to D0-D31 In Invalid (Hold) TS Width Asserted5 TS Width Deasserted Between Consecutive TX Writes8 TS, HA Width Deasserted (Others)11 HS Asserted to TS Deasserted HS Hold Time After TS Deasserted 10 0 -- -- 2 3 -- -- -- -- -- 186 100 -- -- 18 306 100 7 0 -- -- 2 3 -- -- -- -- -- 16 88 -- -- 16 25 88 5 0 -- -- 2 3 -- -- -- -- -- 13.5 74 -- -- 14 20 74 ns ns ns ns ns ns ns ns ns
107
108
--
216
--
20
--
17
ns
109 110 111 112 113 114
8 5 16 -- -- 24 0
-- -- -- 79 12 -- --
6 4 14 -- -- 21 0
-- -- -- 64.5 10 -- --
5 3.5 12 -- -- 17 0
-- -- -- 51.5 9 -- --
ns ns ns ns ns ns ns
2-20
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
Table 2-9 Host Timing (Continued)
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
115 118 120 121 122 123
Note:
HS, HA Deasserted to TS Asserted (Setup) HA Width Asserted (DMA Mode) CLK Low to HR Asserted TS, HA Asserted to HR Deasserted CLK Low to HR Asserted After TS Deassertion12 TS, HA Deasserted to CLK Low (Setup)14
1. 2.
1 24 -- -- 60 13
-- -- 14 30 -- 30
0 21 -- -- 50 11
-- -- 12 25 -- 25
0 18 -- -- 40 9.5
-- -- 10 21 -- 20
ns ns ns ns ns ns
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% Assuming duty cycle in the range 46%-54% When reading status (ICS register), the status data is guaranteed to be stable. 2Tc + 40 2Tc + 38 Assuming both TX and HRX empty 2Tc + Tl + 5 2Tc + Tl + 3 Both TS and HA must be deasserted in case of mixed DMA / non-DMA accesses (i.e., after any access this recovery time must be respected before a new access.) When TS deassertion was in respect to timing 123 2Tc When timing 123 is respected, timing 122 is guaranteed to be respected. Timing 123 is not required for correct operation. Tc
MOTOROLA
DSP96002/D, Rev. 2
2-21
Specifications AC Electrical Characteristics
A2-A5 (input) 102 R/W (input)
107 114
108 HS (input) 101 TS (input) 103 105 D0-D31 (output) 111
115 112
106 104
Figure 2-11 Host Read Cycle Timing (Non-DMA Mode)
A2-A5 (input) 102 R/W (input) 114 113 HS (input) 101 TS (input) 109 D0-D31 (input) 110 111 112 115
Figure 2-12 Host Write Cycle Timing (Non-DMA Mode)
2-22
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
121 HR (output) 118 HA (input) 108 D0-D31 (output) 105 112
106 104
Figure 2-13 Host Read Cycle Timing (DMA Mode)
121 HR (output) 118 HA (input) 109 D0-D31 (input) 110 112
Figure 2-14 Host Write Cycle Timing (DMA Mode)
R/W (input) 107 HA (input) 108
102 114
115 112 111
TS (input) 103
106 104
D0-D31 (output)
105
Figure 2-15 Host Interrupt Vector Register (IVR) Read Timing (Non-DMA Mode)
MOTOROLA
DSP96002/D, Rev. 2
2-23
Specifications AC Electrical Characteristics
CLK (input) 123 TS, HA (input) 122 121 HR (output)
120
Figure 2-16 Host Request Timing
2-24
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
OnCE Timing
Table 2-10 OnCE Timing
No.
1
Characteristic
DSCK Low DSCK High DSCK Cycle Time
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 40 40 240 1525 51 6 17 6 747 819 4011 -- 1015 4 22217 6 -- -- -- -- -- -- -- -- -- -- 6812 0 -- -- -- -- 60 40 40 200 1266 42 5 15 5 61.57 67.510 33.513 -- 816 3 185.518 5 -- -- -- -- -- -- -- -- -- -- 5714 0 -- -- -- -- 60 40 35 160 1056 34 4 13 4 507 5410 27 -- 7 2 14818 4 -- -- -- -- -- -- -- -- -- -- 46 0 -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DR Asserted to DSO (ACK) Asserted DSCK High to DSO Valid DSCK High to DSO Invalid DSI Valid to DSCK Low (Setup) DSCK Low to DSI Invalid (Hold) Last DSCK Low to OS0-OS1, ACK Active DSO (ACK) Asserted to First DSCK High8 DSO (ACK) Width Asserted DSO (ACK) Asserted to OS0-OS1 Tristate OS0-OS1 Valid to CLK High CLK High to OS0-OS1 Invalid Last DSCK Low of Read Register to First DSCK High of Next Command19 Last DSCK Low to DSO Invalid (Hold) DSCK Rise and Fall Times
MOTOROLA
DSP96002/D, Rev. 2
2-25
Specifications AC Electrical Characteristics
Table 2-10 OnCE Timing (Continued)
No.
Note:
1
Characteristic
1. 2.
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% Assuming duty cycle in the range 46%-54% 5Tc + 2 5Tc + 1 2Tc + Tl Tl maximum. 2Tc + Tl + 5 2Tc + Tl + 4 Tc + Tl - 4 2Tc + 8 13. 14. 15. 16. 17. 18. 19. Tc + Tl - 3 2Tc + 7 Tc - 20 Tc - 17 6Tc + Th + 26 6Tc + Th + 22 Th maximum
3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
146 DSCK (input) 130 131 132
146
Figure 2-17 OnCE Serial Clock Timing
DR (input) 133 DSO (output) ACK
Figure 2-18 OnCE Acknowledge Timing
2-26
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
DSCK (input) 134 DSO (output)
(Last) (Note 1) 135 145
(OS1)
(ACK)
DSI (input) 136 137 138
(OS0)
Note: Tri-state, external pull-down resistor
Figure 2-19 OnCE Data I/O to Status Timing
139 OS1 (output) (Note 1) 134 140 DSO (output) (ACK) (DSO output) (DSCK input)
OS0 (output) 141 136 137 (DSI input)
Note: Tri-state, external pull-down resistor
Figure 2-20 OnCE Status to Data I/O Timing
CLK (input) 142 OS0-1 (output) 143
Figure 2-21 OnCE CLK to Status Timing
MOTOROLA
DSP96002/D, Rev. 2
2-27
Specifications AC Electrical Characteristics
DSCK (input) (Read Register) 144 (Next Command)
Figure 2-22 OnCE DSCK Next Command After Read Register Timing
Reset, Mode Select, Interrupt Timing
Table 2-11 Reset, Mode Select, Interrupt Timing
No.1
Characteristic2
RESET Asserted to D0-D31, A0-A31, S0-S1, R/W, BS, TT, TS, BA Threestate RESET Asserted to BL, BR, HR Deasserted RESET Width Asserted5 Asynchronous RESET Deassertion to First External Access Synchronous Reset Setup Time from RESET Deassertion to CLK High Synchronous Reset Delay from CLK High to First External Access7 Mode Select Setup Time Mode Select Hold Time Edge-Triggered Interrupt Request Width Delay from IRQA, IRQB, or IRQC assertion to External Memory Access Out Valid Caused by First Interrupt Instruction Execution6
33.3 MHz3
40 MHz4 Max
6010
60 MHz4 Unit Min
--
Min Max Min
160 -- 709 --
Max
50 ns
161 162 163 164 165 166 167 168
-- 60013 30014 6 24218 50 0 10
10011 -- 36515 2517 25419 -- -- --
-- 50013 25014 5 20218 50 0 10
8512 -- 30516 2017 21220 -- -- --
-- 40013 20014 4 16218 40 0 10
60 -- 24516 1617 170 -- -- --
ns ns ns ns ns ns ns ns
169
28421
--
236.521
--
18921
--
ns
2-28
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
Table 2-11 Reset, Mode Select, Interrupt Timing (Continued)
No.
1
Characteristic
2
33.3 MHz3
40 MHz4 Max
2523
60 MHz4 Unit Min Max
2023
Min Max Min
Delay from A0-A31, S0-S1, R/W, BS, and TT Valid Caused by First Interrupt Instruction Execution to IRQA, IRQB, IRQC Deassertion8
1. 2.
170
--
3022
--
--
ns
Note:
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% and no wait states Assuming duty cycle in the range 46%-54%% and no wait states Assuming stable CLK and VCC Assuming a single-cycle MOVE instruction in the first vector location, interrupting a stream of oneword, single-cycle instructions Assuming BG asserted and BB deasserted
3. 4. 5. 6.
7.
8.
This timing is necessary to prevent multiple interrupt service when the interrupt request is a levelsensitive fast interrupt. To avoid this restriction, Edge-triggered mode is recommended when using fast interrupts and long interrupts are recommended when using Level-sensitive mode Tc + 40 Tc + 35 2Tc + 40 2Tc + 35 20Tc 14. 15. 16. 17. 18. 10Tc 11Tc + 35 11Tc + 30 Tc - 5 8Tc + 2 19. 20. 21. 22. 23. 8Tc + 14 8Tc + 12 9Tc + Tl (WS + 2)Tc - 30 (WS + 2)Tc - 25
9. 10. 11. 12. 13.
MOTOROLA
DSP96002/D, Rev. 2
2-29
Specifications AC Electrical Characteristics
RESET (input) 161 BL, BR, HR (output) D0-D31, A0-A31, S0-S1, R/W, BS, TT, TS, BA (output) 160
162
VIHR
Figure 2-23 Reset Entry Timing
VIHR
RESET (input) 163 Bus Signals (output)
First Fetch
Figure 2-24 Asynchronous Reset Exit Timing
CLK (input) 164 VIHR RESET (input) 165 Bus Signals (output)
First Fetch
Figure 2-25 Synchronous Reset Exit Timing
2-30
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
RESET (input)
162
VIHR
166 MODA, MODB, MODC (input) VIHM VILM
167 VIH IRQA, IRQB, IRQC VIL
Figure 2-26 Operating Mode Select Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, BS, TT (output)
168
169
First Interrupt Instruction Execution
Note: Reset, Mode Select, Interrupt Figure 5
Figure 2-27 External Edge-Triggered Interrupt Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, BS, TT (output) 169 170 First Interrupt Instruction Execution
Figure 2-28 External Level-Sensitive Interrupt Timing
MOTOROLA
DSP96002/D, Rev. 2
2-31
Specifications AC Electrical Characteristics
WAIT, STOP, DMA Request Timing
Table 2-12 WAIT, STOP, DMA Request Timing
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
180 IRQA, IRQB, IRQC Asserted to CLK Low (Setup Time for Synchronous Recovery from WAIT State) CLK Low to External Memory Access Valid (First Interrupt Instruction Fetch After Synchronous Recovery from WAIT State)5 IRQA, IRQB, IRQC Width Asserted (Recovery from WAIT State) IRQA, IRQB, IRQC Asserted to External Memory Access Valid (First Interrupt Instruction Fetch After Asynchronous Recovery from WAIT State)5 IRQA Asserted to CLK Low (Setup Time for Synchronous Recovery from STOP State) CLK Low to External Memory Access Valid (First Instruction Fetch After Synchronous Recovery from STOP State)5 IRQA Width Asserted (Recovery from Stop State) IRQA Asserted to External Memory Access Valid (First Instruction Fetch After Asynchronous Recovery from STOP State)5) DR Asserted to CLK Low (Setup Time for Synchronous Recovery from WAIT or STOP State) 12 30 10 25 8 17 ns
181
4067
4208
338.57 350.59
2717
2819
ns
182
3510
--
3010
--
2010
--
ns
183
4067
46611 338.57 388.512 2717
311
ns
184
8
3013
7
2513
5.5
2013
ns
185
37614
39015 313.514 325.516 25114
261
ns
186
3522
--
3022
--
2522
--
ns
187
37614
43617 313.514 363.518 25114
291
ns
188
8
3013
7
2513
5.5
2013
ns
2-32
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
Table 2-12 WAIT, STOP, DMA Request Timing (Continued)
No.
1
Characteristic
2
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
CLK Low to DSO (ACK) Valid (Enter Debug Mode) * After Synchronous Recovery from STOP State * After Synchronous Recovery from WAIT State DR Asserted to DSO (ACK) Valid (Enter Debug Mode) * After Asynchronous Recovery from STOP State * After Asynchronous Recovery from WAIT State DMA Request Asserted to CLK Low (Setup)6 CLK Low to DMA Request Invalid (Hold)6 CLK Low to External DMA Access Valid DR Assertion Width * To recover from WAIT/STOP * To recover from WAIT/STOP and enter Debug Mode
1. 2.
189
54019 51020
-- --
45019 42520
-- --
30519 29020
-- --
ns ns
190
54019 51020
-- --
45019 42520
-- --
30519 29020
-- --
ns ns
191 192 193
6 2 7621
-- -- --
5 2 63.521
-- -- --
5 1.5 5021
-- -- --
ns ns ns
194
3522 42025
30023 --
2924 35025
25023 --
2324 23525
20023 --
ns ns
Note:
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, GND = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, GND = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% and no wait states. Assuming duty cycle in the range 46%-54%% and no wait states. Assuming bus ownership. IRQ pin internally defined as DMA request. 13Tc + Tl + 2 13Tc + Tl + 14 13Tc + Tl + 12 Tc + 5 14Tc + Tl + 30 14Tc + Tl + 25 Tc 14. 15. 16. 17. 18. 19. 20. 12Tc + Tl + 2 12Tc + Tl + 14 12Tc + Tl + 12 13Tc + Tl + 30 13Tc + Tl + 25 18Tc 17Tc 21. 22. 23. 24. 25. 2Tc + Tl + 2 Tc + 5 10Tc Tc + 4 14Tc
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
MOTOROLA
DSP96002/D, Rev. 2
2-33
Specifications AC Electrical Characteristics
CLK (input) IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, BS, TT (output)
180
181 First Interrupt Instruction Fetch
Figure 2-29 Recovery from WAIT State Using Synchronous Interrupt Timing
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, BS, TT (output)
182
183 First Interrupt Instruction Fetch
Figure 2-30 Recovery from WAIT State Using Asynchronous Interrupt Timing
CLK (input) 184 IRQA (input) A0-A31, S0-S1, R/W, BS, TT (output) 185 First Instruction Fetch
Figure 2-31 Recovery from STOP State Using Synchronous Interrupt Timing
2-34
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
IRQA (input)
186
187 A0-A31, S0-S1, R/W, BS, TT (output) First Instruction Fetch
Figure 2-32 Recovery from STOP State Using Asynchronous Interrupt Timing
CLK (input) 194 DR (input) 188 DSO (output) 189 ACK
Figure 2-33 Recovery from WAIT/STOP State Using Synchronous DR Timing
DR (input)
194
190 DSO (output) ACK
Figure 2-34 Recovery from WAIT/STOP State Using Asynchronous DR Timing
MOTOROLA
DSP96002/D, Rev. 2
2-35
Specifications AC Electrical Characteristics
CLK (input) 192
IRQA, IRQB, IRQC (input) A0-A31, S0-S1, R/W, BS, TT (output)
191 193 DMA Access
Figure 2-35 External DMA Request Timing
Timer/Event Counter
Table 2-13 Timer Timing
No.1
260 261 262 263
Note:
Characteristic2
TIO Low TIO High CKOUT to TIO (output) assertion CKOUT to TIO (output) deassertion
1. 2.
33.3 MHz3
40 MHz4
60 MHz4 Unit
Min Max Min Max Min Max
2Tc 2Tc 2 2 -- -- 18 18 2Tc 2Tc 2 2 -- -- 15 15 2Tc 2Tc 2 2 -- -- 12 12 ns ns ns ns
The numbers in this column are shown as circled numbers in the following figures. DC Electrical Characteristics: at 33.3 MHz: VCC = 5.0 V 10%, VSS = 0 V DC, TJ = -40C to 100C at 40 or 60 MHz: VCC = 5.0 V 5%, VSS = 0 V DC, TJ = -40C to 100C Assuming duty cycle in the range 46.7%-53.3% and no wait states. Assuming duty cycle in the range 46%-54%% and no wait states.
3. 4.
2-36
DSP96002/D, Rev. 2
MOTOROLA
Specifications AC Electrical Characteristics
TIO
261 260
Figure 2-36 TIO Timer Event Input Restrictions
CKOUT
TIO (output)
262 263
Figure 2-37 External Pulse Generation
MOTOROLA
DSP96002/D, Rev. 2
2-37
Specifications AC Electrical Characteristics
2-38
DSP96002/D, Rev. 2
MOTOROLA
SECTION 3 PACKAGING
This section contains package and pin-out information for the DSP96002. There are two package options: 223-pin Pin Grid Array (PGA) or 240-pin Ceramic Quad Flat Pack (CQFP).
MOTOROLA
DSP96002/D, Rev. 2
3-1
Packaging PGA Package
PGA PACKAGE
1 A B C D E F G H J K L M N P R T U V
2
3
4
5
6
7
ABR ABA ABL
8
TIO0 BTT ATT
9
10
11
ATS
12
AAE
13
14
15
16
17
18 A B C D E F G H J K L M N P R T U V
BA23 BA27 BA29 BA31 IRQA ABB BA20 BA25 BA28 BA30 IRQB ABG BA17 BA21 BA26 GNDN IRQC RES BA15 BA18 BA24 BA13 BA16 BA22 GNDN BA12 BA14 BA19 GNDN BA09 BA10 VCCN VCCN BA08 CLK ATA BTA BA11 VCCQ BA07 GNDQ
AR/W AS0 AS1 AWR ABS
AA02 AA04 AA07 AA10 AA13 AA16
AA00 AA03 AA06 AA09 AA11 AA14 AA18 AA20
AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23
GNDN GNDN GNDN VCCN VCCN VCCQ GNDQ VCCN GNDN GNDN GNDN AA22 AA25 AA26 GNDN AA24 AA28 AA29 GNDN AA27 AA30 AD31
BA04 BA05 BA06 VCCN BA03 BA01 BA02 VCCN BA00 BS1 BAE BS0 GNDN GNDN GNDN
DSP96002 223 PIN PGA TOP VIEW
Top View
GNDN AA31 AD30 AD29 VCCN AD28 AD27 AD26 GNDQ AD24 AD25 AD23 GNDQ AD20 AD21 AD22 VCCQ AD16 AD18 AD19 VCCN VCCN ADE AD17
TIO1 BWR BBL BBB AHR
GNDN AD11 AD14 AD15 GNDN AD07 AD12 AD13
BR/W BTS BBS BBG BHR DSO BBR BBA
GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 DR AHS BDE BD31 GNDN BD26 BD22 BD17 BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08 BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04
DSCK NC(1) AHA DSI BHA BHS
BD30 BD28 BD25 BD23 BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 3-1 Top View of the DSP96002 223-pin PGA Package
3-2
DSP96002/D, Rev. 2
MOTOROLA
Packaging PGA Package
1 V U T R P N M L K J H G F E D C B A
DSO BHR BBG BBS
2
DSI
3
BHA
4
BHS
5
6
7
8
9
10
11
12
13
14
15
16
17
18 V U T R P N M L K J H G F E D C B A
BD30 BD28 BD25 BD23 BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01 BDE AHS BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04 BD31 GNDN BD26 BD22 BD17 BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08
DSCK NC(1) AHA BBA BBR AHR BBB BBL BWR BS0 DR
GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 GNDN GNDN GNDN GNDN AD07 AD12 AD13 GNDN AD11 AD14 AD15
BR/W BTS BAE TIO1
BA00 BS1
BA03 BA01 BA02 VCCN BA04 BA05 BA06 VCCN ATA BTA BA07 GNDQ BA11 VCCQ
DSP96002 223 PINS PGA BOTTOM VIEW
Bottom View
VCCN VCCN ADE
AD17
VCCQ AD16 AD18 AD19 GNDQ AD20 AD21 AD22 GNDQ AD24 AD25 AD23 VCCN AD28 AD27 AD26 GNDN AA31 AD30 AD29 GNDN AA27 AA30 AD31 GNDN AA24 AA28 AA29
BA08 CLK
BA09 BA10 VCCN VCCN BA12 BA14 BA19 GNDN BA13 BA16 BA22 GNDN BA15 BA18 BA24
GNDN GNDN GNDN VCCN VCCN VCCQ GNDQ VCCN GNDN GNDN GNDN AA22 AA25 AA26 ABL ABA ABR ATT BTT TIO0 AWR AS1 AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23 ABS AA00 AA03 AA06 AA09 AA11 AA14 AA18 AA20 ATS AAE AA02 AA04 AA07 AA10 AA13 AA16
BA17 BA21 BA26 GNDN IRQC RES BA20 BA25 BA28 BA30 IRQB ABG BA23 BA27 BA29 BA31 IRQA ABB
AR/W AS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 3-2 Bottom View of the DSP96002 223-pin PGA Package
MOTOROLA
DSP96002/D, Rev. 2
3-3
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package
Pin Number
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Output Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Signal Name
BA23 BA27 BA29 BA31 MODA/IRQA ABB ABR TIO0 AR/W AS0 ATS AAE AA02 AA04 AA07 AA10 AA13 AA16 BA20 BA25 BA28 BA30 MODB/IRQB ABG ABA BTT AS1 ABS AA00 AA03 AA06 AA09 AA11 AA14 AA18
3-4
DSP96002/D, Rev. 2
MOTOROLA
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Input Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output
Signal Name
AA20 BA17 BA21 BA26 GNDN MODC/IRQC RESET ABL ATT AWR AA01 AA05 AA08 AA12 AA15 AA17 AA19 AA21 AA23 BA15 BA18 BA24 GNDN GNDN GNDN VCCN VCCN VCCQ GNDN VCCN GNDN GNDN GNDN AA22 AA25 AA26
MOTOROLA
DSP96002/D, Rev. 2
3-5
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
E1 E2 E3 E4 E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H15 H16 H17 H18 J1 J2 J3 J4
Signal Type
Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Input Input/Output Input/Output Input/Output Input Input Input/Output Input
Signal Name
BA13 BA16 BA22 GNDN GNDN AA24 AA28 AA29 BA12 BA14 BA19 GNDN GNDN AA27 AA30 AD31 BA09 BA10 VCCN VCCN GNDN AA31 AD30 AD29 BA08 CLK BA11 VCCQ VCCN AD28 AD27 AD26 ATA BTA BA07 GNDQ
3-6
DSP96002/D, Rev. 2
MOTOROLA
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
J15 J16 J17 J18 K1 K2 K3 K4 K15 K16 K17 K18 L1 L2 L3 L4 L15 L16 L17 L18 M1 M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18
Signal Type
Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Output Output Input Input Input Input Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output
Signal Name
GNDQ AD24 AD25 AD23 BA04 BA05 BA06 VCCN GNDQ AD20 AD21 AD22 BA03 BA01 BA02 VCCN VCCQ AD16 AD18 AD19 BA00 BS1 BS0 GNDN VCCN VCCN ADE AD17 BAE TIO1 BWR GNDN GNDN AD11 AD14 AD15
MOTOROLA
DSP96002/D, Rev. 2
3-7
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
P1 P2 P3 P4 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Signal Type
Input/Output Input/Output Output Input Input Input/Output Input/Output Input/Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Input Output Output Input Input Input/Output Input Input/Output Input/Output Input/Output
Signal Name
BR/W BTS BBL GNDN GNDN AD07 AD12 AD13 BBS BBR BBB GNDN GNDN GNDN VCCN GNDQ VCCQ VCCQ VCCN GNDN GNDN GNDN GNDN AD05 AD09 AD10 BBG BBA AHR DR AHS BD31 GNDN BD26 BD22 BD17
3-8
DSP96002/D, Rev. 2
MOTOROLA
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8
Signal Type
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output N/A Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output
Signal Name
BD14 BD11 BD07 BD04 BD01 AD02 AD06 AD08 BHR DSCK/OS1 NC1 AHA BDE BD29 BD27 BD24 BD21 BD18 BD15 BD12 BD09 BD06 BD03 BD00 AD03 AD04 DSO DSI/OS0 BHA BHS BD30 BD28 BD25 BD23
MOTOROLA
DSP96002/D, Rev. 2
3-9
Packaging PGA Package
Table 3-1 DSP96002 Pin List, 223-pin PGA Package (Continued)
Pin Number
V9 V10 V11 V12 V13 V14 V15 V16 V17 V18
Signal Type
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Signal Name
BD20 BD19 BD16 BD13 BD10 BD08 BD05 BD02 AD00 AD01
-TA -EL
A B C D E F G H J K L M N P R T U V 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
H
G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 1.840 1.880 1.840 1.880 0.120 0.150 0.017 0.020 0.100 BSC 0.050 BSC 0.170 0.190
G
B -F-
H
DIM A B C D G H L
C
223X
D 0.030 M T E S F S 0.010 M T
CASE 860C-02 ISSUE A
Figure 3-3 DSP96002 Mechanical Information, 223-pin PGA Package
3-10
DSP96002/D, Rev. 2
MOTOROLA
Packaging CQFP Package
CQFP PACKAGE
NC NC NC GNDN BA27 BA26 BA25 BA24 VCCN BA23 BA22 BA21 BA20 GNDN BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 GNDN BA11 BA10 BA09 BA08 VCCQ CLK GNDQ VCCN BA07 BTA ATA BA06 BA05 BA04 GNDN BA03 BA02 BA01 BA00 BAE BS1 BS0 BRW TIO1 GNDN BWR BTS BBS VCCN BBL BBR BBG BBB NC NC NC NC 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181
NC NC NC BA28 BA29 BA30 BA31 MODC MODB MODA RES ABG ABB ABR ABA ABL GNDN TIO0 VCCN BTT ATT ARW AWR GNDN AS1 AS0 ATS ABS AAE AA00 AA01 AA02 AA03 GNDN AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21 NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Orientation Mark
(Top View)
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
NC NC NC BBA GNDN BHR AHR DSO DSCK DSI DR NC BHA AHA BHS AHS BDE BD31 BD30 BD29 BD28 GNDN BD27 BD26 BD25 BD24 VCCN BD23 BD22 BD21 BD20 GNDN BD19 BD18 BD17 BD16 VCCQ GNDQ BD15 BD14 BD13 BD12 GNDN BD11 BD10 BD09 BD08 VCCN BD07 BD06 BD05 BD04 GNDN BD03 BD02 BD01 BD00 NC NC NC
MOTOROLA
NC NC NC AA22 AA23 VCCN AA24 AA25 AA26 AA27 GNDN AA28 AA29 AA30 AA31 AD31 AD30 AD29 AD28 GNDN AD27 AD26 AD25 AD24 VCCN AD23 AD22 AD21 AD20 GNDN AD19 AD18 AD17 AD16 VCCQ GNDQ AD15 /ADE AD14 AD13 AD12 GNDN AD11 AD10 AD09 AD08 VCCN AD07 AD06 AD05 AD04 GNDN AD03 AD02 AD01 AD00 NC NC NC NC
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Figure 3-4 Top View of the DSP96002 240-pin CQFP Package
DSP96002/D, Rev. 2
3-11
Packaging CQFP Package
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
NC NC NC NC BBB BBG BBR BBL VCCN BBS BTS BWR GNDN TIO1 BRW BS0 BS1 BAE BA00 BA01 BA02 BA03 GNDN BA04 BA05 BA06 ATA BTA BA07 VCCN GNDQ CLK VCCQ BA08 BA09 BA10 BA11 GNDN BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 GNDN BA20 BA21 BA22 BA23 VCCN BA24 BA25 BA26 BA27 GNDN NC NC NC
NC NC NC BBA GNDN BHR AHR DSO DSCK DSI DR NC BHA AHA BHS AHS BDE BD31 BD30 BD29 BD28 GNDN BD27 BD26 BD25 BD24 VCCN BD23 BD22 BD21 BD20 GNDN BD19 BD18 BD17 BD16 VCCQ GNDQ BD15 BD14 BD13 BD12 GNDN BD11 BD10 BD09 BD08 VCCN BD07 BD06 BD05 BD04 GNDN BD03 BD02 BD01 BD00 NC NC NC
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
Orientation Mark (on top side)
(Bottom View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
NC NC NC BA28 BA29 BA30 BA31 MODC MODB MODA RES ABG ABB ABR ABA ABL GNDN TIO0 VCCN BTT ATT ARW AWR GNDN AS1 AS0 ATS ABS AAE AA00 AA01 AA02 AA03 GNDN AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21 NC NC NC
3-12
NC NC NC NC AD00 AD01 AD02 AD03 GNDN AD04 AD05 AD06 AD07 VCCN AD08 AD09 AD10 AD11 GNDN AD12 AD13 AD14 /ADE AD15 GNDQ VCCQ AD16 AD17 AD18 AD19 GNDN AD20 AD21 AD22 AD23 VCCN AD24 AD25 AD26 AD27 GNDN AD28 AD29 AD30 AD31 AA31 AA30 AA29 AA28 GNDN AA27 AA26 AA25 AA24 VCCN AA23 AA22 NC NC NC
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
Figure 3-5 Bottom View of the DSP96002 240-pin CQFP Package
DSP96002/D, Rev. 2
MOTOROLA
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Signal Type
N/A N/A N/A Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Output Output Output Input Input/Output Input Output Output Output Output Input Output Output Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Input NC NC NC
Signal Name
BA28 BA29 BA30 BA31 IRQC/MODC IRQB/MODB IRQA/MODA RESET ABG ABB ABR ABA ABL GNDN TIO0 VCCN BTT ATT AR/W AWR GNDN AS1 AS0 ATS ABS AAE AA00 AA01 AA02 AA03 GNDN
MOTOROLA
DSP96002/D, Rev. 2
3-13
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Signal Type
Input/Output Input/Output Input/Output Input/Output Input Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output N/A N/A N/A N/A N/A N/A Input/Output Input/Output Input Input/Output Input/Output Input/Output
Signal Name
AA04 AA05 AA06 AA07 GNDQ VCCQ VCCN AA08 AA09 AA10 AA11 GNDN AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 GNDN AA20 AA21 NC NC NC NC NC NC AA22 AA23 VCCN AA24 AA25 AA26
3-14
DSP96002/D, Rev. 2
MOTOROLA
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
Signal Type
Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input Input/Output Input/Output Input/Output Input Input/Output
Signal Name
AA27 GNDN AA28 AA29 AA30 AA31 AD31 AD30 AD29 AD28 GNDN AD27 AD26 AD25 AD24 VCCN AD23 AD22 AD21 AD20 GNDN AD19 AD18 AD17 AD16 VCCQ GNDQ AD15 ADE AD14 AD13 AD12 GNDN AD11
MOTOROLA
DSP96002/D, Rev. 2
3-15
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
Signal Type
Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output N/A N/A N/A N/A N/A N/A N/A Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output
Signal Name
AD10 AD09 AD08 VCCN AD07 AD06 AD05 AD04 GNDN AD03 AD02 AD01 AD00 NC NC NC NC NC NC NC BD00 BD01 BD02 BD03 GNDN BD04 BD05 BD06 BD07 VCCN BD08 BD09 BD10 BD11 GNDN BD12
3-16
DSP96002/D, Rev. 2
MOTOROLA
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Signal Type
Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input N/A Input Input/Output Input/Output Output Output Output
Signal Name
BD13 BD14 BD15 GNDQ VCCQ BD16 BD17 BD18 BD19 GNDN BD20 BD21 BD22 BD23 VCCN BD24 BD25 BD26 BD27 GNDN BD28 BD29 BD30 BD31 BDE AHS BHS AHA BHA NC DR DSI/OS0 DSK/OS1 DSO AHR BHR
MOTOROLA
DSP96002/D, Rev. 2
3-17
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Signal Type
Input Output N/A N/A N/A N/A N/A N/A N/A Input Input Output Output Input Output Input/Output Output Input Input/Output Output Output Output Input Output Output Output Output Input Output Output Output Input Input Output Input
Signal Name
GNDN BBA NC NC NC NC NC NC NC BBB BBG BBR BBL VCCN BBS BTS BWR GNDN TIO1 BR/W BS0 BS1 BAE BA00 BA01 BA02 BA03 GNDN BA04 BA05 BA06 ATA BTA BA07 VCCN
3-18
DSP96002/D, Rev. 2
MOTOROLA
Packaging CQFP Package
Table 3-2 DSP96002 Pin List, 240-pin CQFP Package (Continued)
Pin Number
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Signal Type
Input Input Input Output Output Output Output Input Output Output Output Output Output Output Output Output Input Output Output Output Output Input Output Output Output Output Input N/A N/A N/A
Signal Name
GNDQ CLK VCCQ BA08 BA09 BA10 BA11 GNDN BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 GNDN BA20 BA21 BA22 BA23 VCCN BA24 BA25 BA26 BA27 GNDN NC NC NC
MOTOROLA
DSP96002/D, Rev. 2
3-19
Packaging CQFP Package
S U
180 121
VIEW AC
4 PLACES 120
AD AD G P X
181
Y VIEW AC L V N B F
X = L, M OR N
Z
J
D
240 61
0.08 M T L-N M SECTION AD
1
M A
60
240 PLACES NOTES: 1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEADS WHERE THEY EXIT THE BODY. 1. 4. DATUMS L, M, AND N TO BE DETERMINED AT DATUM PLANE H. 2. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE DATUM T. 3. 6. DIMENSIONS A AND B DEFINE MAXIMUM CERAMIC BODY DIMENSIONS INCLUDING GLASS PROTRUSION AND TOP AND BOTTOM MISMATCH.
4X 6 0 TIPS
0.30 T L-N M C E
0.20 M H L-N M VIEW AE
H
T
SEATING PLANE
W
0.10 T
DIM A B C D E F G J K P R S U V W Y Z AA AB 1 2
(AB) 1 R 2 (R) K (AA) VIEW AE
CASE 988-01 ISSUE E
MILLIMETERS MIN MAX 30.86 31.75 30.86 31.75 3.75 4.15 0.18 0.30 3.10 3.90 0.17 0.23 0.50 BSC 0.13 0.175 0.45 0.55 0.25 BSC 0.15 BSC 34.60 BSC 17.30 BSC 34.60 BSC 0.04 0.24 17.30 BSC 0.12 0.13 1.80 REF 0.95 REF 6 2 1 7
Figure 3-6 DSP96002 Mechanical Information, 240-pin CQFP Package
3-20
DSP96002/D, Rev. 2
MOTOROLA
Packaging Package and Pin-Out Information
PACKAGE AND PIN-OUT INFORMATION
Complete mechanical information regarding DSP96002 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information: * * The receiving facsimile telephone number including area code or country code The caller's Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - - Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages
A total of three documents may be ordered per call. The mechanical drawings for the 223-pin PGA package are referenced as 860C-02. The mechanical drawings for the 240-pin CQFP package are referenced as 988-01.
MOTOROLA
DSP96002/D, Rev. 2
3-21
Packaging Package and Pin-Out Information
3-22
DSP96002/D, Rev. 2
MOTOROLA
SECTION 4 DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-tocase thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.
MOTOROLA
DSP96002/D, Rev. 2
4-1
Design Considerations Thermal Design Considerations
The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
*
*
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface, and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4-2
DSP96002/D, Rev. 2
MOTOROLA
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation: * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5" per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses, as well as the IRQA, IRQB, IRQC, TA, TS, BG, HS, and HA pins. Maximum PCB trace lengths on the order of 6" are recommended. Consider all device loads, as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the VCCPLL and VSSPLL pins.
*
* *
*
* *
MOTOROLA
DSP96002/D, Rev. 2
4-3
Design Considerations Power Consumption Considerations
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors that affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the formula: Equation 3: I = C x V x f where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle Example 4-1 Current Consumption
For an I/O pin loaded with 50 pF capacitance, operating at 5.5 V, and with a 60 MHz clock, toggling at its maximum possible rate (30 MHz), the current consumption is:
Equation 4:
I = 50 x 10
- 12
x 5.5 x 30 x 10 = 8.25 mA
6
The Maximum Internal Current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The Typical Internal Current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption: * * * * * Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. Disable unused pin activity.
4-4
DSP96002/D, Rev. 2
MOTOROLA
Design Considerations Power-Up Considerations
POWER-UP CONSIDERATIONS
To power-up the device properly, ensure that the following conditions are met: * * * Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). The external clock oscillator is active and stable. RESET is asserted according to the specifications in Table 2-7 (Reset, Stop, Mode Select, and Interrupt Timing).
Care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on Table 2-1 (Maximum Ratings), at all phases of the powerup procedure. This may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state.
MOTOROLA
DSP96002/D, Rev. 2
4-5
Design Considerations Power-Up Considerations
4-6
DSP96002/D, Rev. 2
MOTOROLA
SECTION 5 ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information
Part Supply Voltage Package Type Pin Count Frequency (MHz) 60 Pin Grid Array (PGA) DSP96002 5V Ceramic Quad Flat Pack (CQFP) 240 40 DSP96002FE40 223 40 33 60 Order Number DSP96002RC60 DSP96002RC40 DSP96002RC33 DSP96002FE60
MOTOROLA
DSP96002/D, Rev. 2
5-1
Ordering Information
5-2
DSP96002/D, Rev. 2
MOTOROLA
APPENDIX A BOOTSTRAP CODE FOR DSP96002
; BOOTSTRAP CODE FOR DSP96002 - (c) Copyright 1988 Motorola Inc. ; ; Host algorithm / AND / external bus method. ; ; This is the Bootstrap program contained in the DSP96002. This program ; can load the internal program memory from one of 4 external sources. ; The program reads the OMR bits MA and MB to decide which external ; source to access. ; If MB:MA = 0X - load from 4,096 consecutive byte-wide P: memory ; locations (starting at P:$FFFF0000). ; If MB:MA = 10 - load internal PRAM thru Host Interface in Port A. ; If MB:MA = 11 - load internal PRAM thru Host Interface in Port B. BOOT EQU $FFFF0000; The location in P: memory ; where the external byte-wide ; EPROM is expected to be mapped M_HCRA EQU $FFFFFFEC; Port A Host Control Register M_HSRA EQU $FFFFFFED; Port A Host Status Register M_HRXA EQU $FFFFFFEF; Port A Host Rec. Data Register M_HCRB EQU $FFFFFFE4; Port B Host Control Register M_HSRB EQU $FFFFFFE5; Port B Host Status Register M_HRXB EQU $FFFFFFE7; Port B Host Rec. Data Register ORG PL:$0; bootstrap code starts at P:$0 START MOVE #BOOT,R1; R1 = External P: address of ; bootstrap byte-wide ROM MOVEI #0,R0 ; R0 = starting P: address of ; internal memory where program ; will begin loading. ; If this program is entered by changing the OMR to bootstrap mode, ; make certain that registers M0 and M1 have been set to $FFFFFFFF. ; Make sure the appropriate BCR register is set to $xxxxxxFx since ; EPROMs are slow. ; Make sure that the Port Selection Register is set to permit program ; memory accesses thru the required memory expansion port (Port A or B). ; ; The first routine will load 4,096 bytes from the external P memory ; space beginning at P:$FFFF0000 (bits 7-0). These will be condensed ; into 1,024 32-bit words and stored in contiguous internal PRAM memory ; locations starting at P:$0. Note that the first routine loads data ; starting with the least significant byte of P:$0 first. ; The Port Selection Register is not set by this program. It is set ; by HW Reset.
MOTOROLA
DSP96002/D, Rev. 2
A-1
Bootstrap Code for DSP96002
; ; ; ; ; ; ; ; ; ; ; ; ;
The second routine loads the internal PRAM using the Host Interface logic. If HF1=0, it will load 4,096 bytes from the external host processor. These will be condensed into 1,024 32-bit words and stored in contiguous internal PRAM memory locations starting at P:$0. Note that the routine loads data starting with the least significant byte of P:$0 first. If HF1=1, it will load 1,024 32-bit words from the external host processor. If the host processor only wants to load a portion of the P memory, and start execution of the loaded program, the Host Interface bootstrap load program routine may be killed by setting HF0 = 0.
INLOOP DO #1024,_LOOP1; Load 1,024 instruction words ; This is the context switch JSET #1,OMR,_HOSTLD; Perform load from Host ; Interface if MB=1. ; This is the first routine. It loads from external P: memory. DO #4,_LOOP2; Get 4 bytes into D0.L LSR #8,D0; Shift previous byte down MOVEM P:(R1)+,D1.L; Get byte from ext. P mem. LSL #24,D1; Shift into upper byte OR D1,D0; concatenate _LOOP2 JMP <_STORE; Then put the word in P memory ; ; This is the second routine. It loads thru the Host Interface. _HOSTLD JSET #0,OMR,_HOSTB; Port A or Port B? ; Boot thru Host Interface in Port A _HOSTA BCLR #5,X:M_HCRA; Enable Port A Host Interface MOVE #M_HSRA,R2; R2 points to HSRA MOVE #M_HRXA,R3; R3 points to HRXA JMP <_HOSTR; go to host routine ; Boot thru Host Interface in Port B _HOSTB BCLR #5,X:M_HCRB; Enable Port B Host Interface MOVE #M_HSRB,R2; R2 points to HSRB MOVE #M_HRXB,R3; R3 points to HRXB
A-2
DSP96002/D, Rev. 2
MOTOROLA
Bootstrap Code for DSP96002
; Host load routine _HOSTR _LBL11 JCLR #3,X:(R2),_LBL22; if HF0=1, stop loading data. ENDDO ; Must terminate the do loops JMP <_BOOTEND _LBL22 JCLR JCLR MOVE JMP _LBL33 DO LSR JCLR ENDDO ENDDO JMP JCLR MOVE LSL OR _LOOP4 _STORE _LOOP1 MOVEM D0.L,P:(R0)+ ; Store 32-bit result in P mem. ; and go get another 32-bit word #0,X:(R2),_LBL11; Wait for HRDF to go high ; (meaning data is present). #4,X:(R2),_LBL33; 8-bit source? X:(R3),D0.L; Get 32-bit word from host <_STORE #4,_LOOP4; Get 4 bytes into D0.L #8,D0; Shift previous byte down #3,X:(R2),_LBL2; if HF0=1, stop loading data. ; Must terminate the do loops <_BOOTEND #0,X:(R2),_LBL1; Wait for HRDF to go high ; (meaning data is present). X:(R3),D1.L; Get byte from host #24,D1; Shift into upper byte D1,D0; concatenate
_LBL1
_LBL2
; This is the exit handler that returns execution to internal PRAM _BOOTEND ANDI #$F9,OMR ; Set the operating mode to 00x ; (and trigger an exit from ; bootstrap mode). ANDI #$0,CCR; Clear CCR as if HW RESET. ; Also delay needed for ; Op. Mode change. JMP <$0; Start fetching from PRAM. ; DSP96002 bootstrap program size = 50 words
MOTOROLA
DSP96002/D, Rev. 2
A-3
Bootstrap Code for DSP96002
A-4
DSP96002/D, Rev. 2
MOTOROLA
APPENDIX B X AND Y MEMORY ROM TABLES
Table B-1 X Memory ROM Contents (full cycle of cosine values)
xr:$00000400= $3f800000 xr:$00000404= $3f7fec43 xr:$00000408= $3f7fb10f xr:$0000040c= $3f7f4e6d xr:$00000410= $3f7ec46d xr:$00000414= $3f7e1324 xr:$00000418= $3f7d3aac xr:$0000041c= $3f7c3b28 xr:$00000420= $3f7b14be xr:$00000424= $3f79c79d xr:$00000428= $3f7853f8 xr:$0000042c= $3f76ba07 xr:$00000430= $3f74fa0b xr:$00000434= $3f731447 xr:$00000438= $3f710908 xr:$0000043c= $3f6ed89e xr:$00000440= $3f6c835e xr:$00000444= $3f6a09a7 xr:$00000448= $3f676bd8 xr:$0000044c= $3f64aa59 xr:$00000450= $3f61c598 xr:$00000454= $3f5ebe05 xr:$00000458= $3f5b941a xr:$0000045c= $3f584853 xr:$00000460= $3f54db31 xr:$00000464= $3f514d3d xr:$00000468= $3f4d9f02 xr:$0000046c= $3f49d112 xr:$00000470= $3f45e403 xr:$00000474= $3f41d870 $3f7ffec4 $3f7fe129 $3f7f9c18 $3f7f2f9d $3f7e9bc9 $3f7de0b1 $3f7cfe73 $3f7bf531 $3f7ac516 $3f796e4e $3f77f110 $3f764d97 $3f748422 $3f7294f8 $3f708066 $3f6e46be $3f6be858 $3f696591 $3f66becc $3f63f473 $3f6106f2 $3f5df6be $3f5ac450 $3f577026 $3f53fac3 $3f5064af $3f4cae79 $3f48d8b3 $3f44e3f5 $3f40d0da $3f7ffb11 $3f7fd397 $3f7f84ab $3f7f0e58 $3f7e70b0 $3f7dabcc $3f7cbfc9 $3f7baccd $3f7a7302 $3f791298 $3f778bc5 $3f75dec6 $3f740bdd $3f721352 $3f6ff573 $3f6db293 $3f6b4b0c $3f68bf3c $3f660f88 $3f633c5a $3f604621 $3f5d2d53 $3f59f26a $3f5695e5 $3f531849 $3f4f7a1f $3f4bbbf8 $3f47de65 $3f43e200 $3f3fc767 $3f7ff4e6 $3f7fc38f $3f7f6ac7 $3f7eea9d $3f7e4323 $3f7d7474 $3f7c7eb0 $3f7b61fc $3f7a1e84 $3f78b47b $3f772417 $3f756d97 $3f73913f $3f718f57 $3f6f6830 $3f6d1c1d $3f6aab7b $3f6816a8 $3f655e0b $3f628210 $3f5f8327 $3f5c61c7 $3f591e6a $3f55b993 $3f5233c6 $3f4e8d90 $3f4ac77f $3f46e22a $3f42de29 $3f3ebc1b
MOTOROLA
DSP96002/D, Rev. 2
B-1
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$00000478= $3f3daef9 xr:$0000047c= $3f396842 xr:$00000480= $3f3504f3 xr:$00000484= $3f3085bb xr:$00000488= $3f2beb4a xr:$0000048c= $3f273656 xr:$00000490= $3f226799 xr:$00000494= $3f1d7fd1 xr:$00000498= $3f187fc0 xr:$0000049c= $3f13682a xr:$000004a0= $3f0e39da xr:$000004a4= $3f08f59b xr:$000004a8= $3f039c3d xr:$000004ac= $3efc5d27 xr:$000004b0= $3ef15aea xr:$000004b4= $3ee63375 xr:$000004b8= $3edae880 xr:$000004bc= $3ecf7bca xr:$000004c0= $3ec3ef15 xr:$000004c4= $3eb8442a xr:$000004c8= $3eac7cd4 xr:$000004cc= $3ea09ae5 xr:$000004d0= $3e94a031 xr:$000004d4= $3e888e93 xr:$000004d8= $3e78cfcc xr:$000004dc= $3e605c13 xr:$000004e0= $3e47c5c2 xr:$000004e4= $3e2f10a2 xr:$000004e8= $3e164083 xr:$000004ec= xr:$000004f0= xr:$000004f4= xr:$000004f8= xr:$000004fc= $3dfab273 $3dc8bd36 $3d96a905 $3d48fb30 $3cc90ab0 $3f3ca003 $3f385216 $3f33e7bc $3f2f61a5 $3f2ac082 $3f26050a $3f212ff9 $3f1c420c $3f173c07 $3f121eb0 $3f0cead0 $3f07a136 $3f0242b1 $3ef9a02d $3eee9479 $3ee363fa $3ed8106b $3ecc9b8b $3ec1071e $3eb554ec $3ea986c4 $3e9d9e78 $3e919ddd $3e8586ce $3e72b651 $3e5a3997 $3e419b37 $3e28defc $3e1008b7 $3dee3876 $3dbc3ac3 $3d8a200a $3d2fe007 $3c96c9b6 $bbc90f88 $bcfb49ba $bd621469 $3f3b8f3b $3f373a23 $3f32c8c9 $3f2e3bde $3f299415 $3f24d225 $3f1ff6cb $3f1b02c6 $3f15f6d9 $3f10d3cd $3f0b9a6b $3f064b82 $3f00e7e4 $3ef6e0cb $3eebcbbb $3ee0924f $3ed53641 $3ec9b953 $3ebe1d4a $3eb263ef $3ea68f12 $3e9aa086 $3e8e9a22 $3e827dc0 $3e6c9a7f $3e541501 $3e3b6ecf $3e22abb6 $3e09cf86 $3de1bc2e $3dafb680 $3d7b2b74 $3d16c32c $3c490e90 $bc490e90 $bd16c32c $bd7b2b74 $3f3a7ca4 $3f36206c $3f31a81d $3f2d1469 $3f286605 $3f239da9 $3f1ebc12 $3f19c200 $3f14b039 $3f0f8784 $3f0a48ad $3f04f484 $3eff17b2 $3ef41f07 $3ee900b7 $3eddbe79 $3ed25a09 $3ec6d529 $3ebb31a0 $3eaf713a $3ea395c5 $3e97a117 $3e8b9507 $3e7ee6e1 $3e667c66 $3e4dee60 $3e354098 $3e1c76de $3e039502 $3dd53db9 $3da3308c $3d621469 $3cfb49ba $3bc90f88 $bc96c9b6 $bd2fe007 $bd8a200a
xr:$00000500= $248d4000 xr:$00000504= $bcc90ab0 xr:$00000508= $bd48fb30
B-2
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$0000050c= $bd96a905 xr:$00000510= $bdc8bd36 xr:$00000514= $bdfab273 xr:$00000518= $be164083 xr:$0000051c= $be2f10a2 xr:$00000520= $be47c5c2 xr:$00000524= $be605c13 xr:$00000528= $be78cfcc xr:$0000052c= $be888e93 xr:$00000530= $be94a031 xr:$00000534= $bea09ae5 xr:$00000538= $beac7cd4 xr:$0000053c= $beb8442a xr:$00000540= $bec3ef15 xr:$00000544= $becf7bca xr:$00000548= $bedae880 xr:$0000054c= $bee63375 xr:$00000550= $bef15aea xr:$00000554= $befc5d27 xr:$00000558= $bf039c3d xr:$0000055c= $bf08f59b xr:$00000560= $bf0e39da xr:$00000564= $bf13682a xr:$00000568= $bf187fc0 xr:$0000056c= $bf1d7fd1 xr:$00000570= $bf226799 xr:$00000574= $bf273656 xr:$00000578= $bf2beb4a xr:$0000057c= $bf3085bb xr:$00000580= $bf3504f3 xr:$00000584= $bf396842 xr:$00000588= $bf3daef9 xr:$0000058c= $bf41d870 xr:$00000590= $bf45e403 xr:$00000594= $bf49d112 xr:$00000598= $bf4d9f02 xr:$0000059c= $bf514d3d $bda3308c $bdd53db9 $be039502 $be1c76de $be354098 $be4dee60 $be667c66 $be7ee6e1 $be8b9507 $be97a117 $bea395c5 $beaf713a $bebb31a0 $bec6d529 $bed25a09 $beddbe79 $bee900b7 $bef41f07 $beff17b2 $bf04f484 $bf0a48ad $bf0f8784 $bf14b039 $bf19c200 $bf1ebc12 $bf239da9 $bf286605 $bf2d1469 $bf31a81d $bf36206c $bf3a7ca4 $bf3ebc1b $bf42de29 $bf46e22a $bf4ac77f $bf4e8d90 $bf5233c6 $bdafb680 $bde1bc2e $be09cf86 $be22abb6 $be3b6ecf $be541501 $be6c9a7f $be827dc0 $be8e9a22 $be9aa086 $bea68f12 $beb263ef $bebe1d4a $bec9b953 $bed53641 $bee0924f $beebcbbb $bef6e0cb $bf00e7e4 $bf064b82 $bf0b9a6b $bf10d3cd $bf15f6d9 $bf1b02c6 $bf1ff6cb $bf24d225 $bf299415 $bf2e3bde $bf32c8c9 $bf373a23 $bf3b8f3b $bf3fc767 $bf43e200 $bf47de65 $bf4bbbf8 $bf4f7a1f $bf531849 $bdbc3ac3 $bdee3876 $be1008b7 $be28defc $be419b37 $be5a3997 $be72b651 $be8586ce $be919ddd $be9d9e78 $bea986c4 $beb554ec $bec1071e $becc9b8b $bed8106b $bee363fa $beee9479 $bef9a02d $bf0242b1 $bf07a136 $bf0cead0 $bf121eb0 $bf173c07 $bf1c420c $bf212ff9 $bf26050a $bf2ac082 $bf2f61a5 $bf33e7bc $bf385216 $bf3ca003 $bf40d0da $bf44e3f5 $bf48d8b3 $bf4cae79 $bf5064af $bf53fac3
MOTOROLA
DSP96002/D, Rev. 2
B-3
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$000005a0= $bf54db31 xr:$000005a4= $bf584853 xr:$000005a8= $bf5b941a xr:$000005ac= $bf5ebe05 xr:$000005b0= $bf61c598 xr:$000005b4= $bf64aa59 xr:$000005b8= $bf676bd8 xr:$000005bc= $bf6a09a7 xr:$000005c0= $bf6c835e xr:$000005c4= $bf6ed89e xr:$000005c8= $bf710908 xr:$000005cc= $bf731447 xr:$000005d0= $bf74fa0b xr:$000005d4= $bf76ba07 xr:$000005d8= $bf7853f8 xr:$000005dc= $bf79c79d xr:$000005e0= $bf7b14be xr:$000005e4= $bf7c3b28 xr:$000005e8= $bf7d3aac xr:$000005ec= xr:$000005f0= xr:$000005f4= xr:$000005f8= xr:$000005fc= $bf7e1324 $bf7ec46d $bf7f4e6d $bf7fb10f $bf7fec43 $bf55b993 $bf591e6a $bf5c61c7 $bf5f8327 $bf628210 $bf655e0b $bf6816a8 $bf6aab7b $bf6d1c1d $bf6f6830 $bf718f57 $bf73913f $bf756d97 $bf772417 $bf78b47b $bf7a1e84 $bf7b61fc $bf7c7eb0 $bf7d7474 $bf7e4323 $bf7eea9d $bf7f6ac7 $bf7fc38f $bf7ff4e6 $bf7ffec4 $bf7fe129 $bf7f9c18 $bf7f2f9d $bf7e9bc9 $bf7de0b1 $bf7cfe73 $bf7bf531 $bf7ac516 $bf796e4e $bf77f110 $bf764d97 $bf748422 $bf5695e5 $bf59f26a $bf5d2d53 $bf604621 $bf633c5a $bf660f88 $bf68bf3c $bf6b4b0c $bf6db293 $bf6ff573 $bf721352 $bf740bdd $bf75dec6 $bf778bc5 $bf791298 $bf7a7302 $bf7baccd $bf7cbfc9 $bf7dabcc $bf7e70b0 $bf7f0e58 $bf7f84ab $bf7fd397 $bf7ffb11 $bf7ffb11 $bf7fd397 $bf7f84ab $bf7f0e58 $bf7e70b0 $bf7dabcc $bf7cbfc9 $bf7baccd $bf7a7302 $bf791298 $bf778bc5 $bf75dec6 $bf740bdd $bf577026 $bf5ac450 $bf5df6be $bf6106f2 $bf63f473 $bf66becc $bf696591 $bf6be858 $bf6e46be $bf708066 $bf7294f8 $bf748422 $bf764d97 $bf77f110 $bf796e4e $bf7ac516 $bf7bf531 $bf7cfe73 $bf7de0b1 $bf7e9bc9 $bf7f2f9d $bf7f9c18 $bf7fe129 $bf7ffec4 $bf7ff4e6 $bf7fc38f $bf7f6ac7 $bf7eea9d $bf7e4323 $bf7d7474 $bf7c7eb0 $bf7b61fc $bf7a1e84 $bf78b47b $bf772417 $bf756d97 $bf73913f
xr:$00000600= $bf800000 xr:$00000604= $bf7fec43 xr:$00000608= $bf7fb10f xr:$0000060c= $bf7f4e6d xr:$00000610= $bf7ec46d xr:$00000614= $bf7e1324 xr:$00000618= $bf7d3aac xr:$0000061c= $bf7c3b28 xr:$00000620= $bf7b14be xr:$00000624= $bf79c79d xr:$00000628= $bf7853f8 xr:$0000062c= $bf76ba07 xr:$00000630= $bf74fa0b
B-4
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$00000634= $bf731447 xr:$00000638= $bf710908 xr:$0000063c= $bf6ed89e xr:$00000640= $bf6c835e xr:$00000644= $bf6a09a7 xr:$00000648= $bf676bd8 xr:$0000064c= $bf64aa59 xr:$00000650= $bf61c598 xr:$00000654= $bf5ebe05 xr:$00000658= $bf5b941a xr:$0000065c= $bf584853 xr:$00000660= $bf54db31 xr:$00000664= $bf514d3d xr:$00000668= $bf4d9f02 xr:$0000066c= $bf49d112 xr:$00000670= $bf45e403 xr:$00000674= $bf41d870 xr:$00000678= $bf3daef9 xr:$0000067c= $bf396842 xr:$00000680= $bf3504f3 xr:$00000684= $bf3085bb xr:$00000688= $bf2beb4a xr:$0000068c= $bf273656 xr:$00000690= $bf226799 xr:$00000694= $bf1d7fd1 xr:$00000698= $bf187fc0 xr:$0000069c= $bf13682a xr:$000006a0= $bf0e39da xr:$000006a4= $bf08f59b xr:$000006a8= $bf039c3d xr:$000006ac= $befc5d27 xr:$000006b0= $bef15aea xr:$000006b4= $bee63375 xr:$000006b8= $bedae880 xr:$000006bc= $becf7bca xr:$000006c0= $bec3ef15 xr:$000006c4= $beb8442a $bf7294f8 $bf708066 $bf6e46be $bf6be858 $bf696591 $bf66becc $bf63f473 $bf6106f2 $bf5df6be $bf5ac450 $bf577026 $bf53fac3 $bf5064af $bf4cae79 $bf48d8b3 $bf44e3f5 $bf40d0da $bf3ca003 $bf385216 $bf33e7bc $bf2f61a5 $bf2ac082 $bf26050a $bf212ff9 $bf1c420c $bf173c07 $bf121eb0 $bf0cead0 $bf07a136 $bf0242b1 $bef9a02d $beee9479 $bee363fa $bed8106b $becc9b8b $bec1071e $beb554ec $bf721352 $bf6ff573 $bf6db293 $bf6b4b0c $bf68bf3c $bf660f88 $bf633c5a $bf604621 $bf5d2d53 $bf59f26a $bf5695e5 $bf531849 $bf4f7a1f $bf4bbbf8 $bf47de65 $bf43e200 $bf3fc767 $bf3b8f3b $bf373a23 $bf32c8c9 $bf2e3bde $bf299415 $bf24d225 $bf1ff6cb $bf1b02c6 $bf15f6d9 $bf10d3cd $bf0b9a6b $bf064b82 $bf00e7e4 $bef6e0cb $beebcbbb $bee0924f $bed53641 $bec9b953 $bebe1d4a $beb263ef $bf718f57 $bf6f6830 $bf6d1c1d $bf6aab7b $bf6816a8 $bf655e0b $bf628210 $bf5f8327 $bf5c61c7 $bf591e6a $bf55b993 $bf5233c6 $bf4e8d90 $bf4ac77f $bf46e22a $bf42de29 $bf3ebc1b $bf3a7ca4 $bf36206c $bf31a81d $bf2d1469 $bf286605 $bf239da9 $bf1ebc12 $bf19c200 $bf14b039 $bf0f8784 $bf0a48ad $bf04f484 $beff17b2 $bef41f07 $bee900b7 $beddbe79 $bed25a09 $bec6d529 $bebb31a0 $beaf713a
MOTOROLA
DSP96002/D, Rev. 2
B-5
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$000006c8= $beac7cd4 xr:$000006cc= $bea09ae5 xr:$000006d0= $be94a031 xr:$000006d4= $be888e93 xr:$000006d8= $be78cfcc xr:$000006dc= $be605c13 xr:$000006e0= $be47c5c2 xr:$000006e4= $be2f10a2 xr:$000006e8= $be164083 xr:$000006ec= xr:$000006f0= xr:$000006f4= xr:$000006f8= xr:$000006fc= $bdfab273 $bdc8bd36 $bd96a905 $bd48fb30 $bcc90ab0 $bea986c4 $be9d9e78 $be919ddd $be8586ce $be72b651 $be5a3997 $be419b37 $be28defc $be1008b7 $bdee3876 $bdbc3ac3 $bd8a200a $bd2fe007 $bc96c9b6 $3bc90f88 $3cfb49ba $3d621469 $3da3308c $3dd53db9 $3e039502 $3e1c76de $3e354098 $3e4dee60 $3e667c66 $3e7ee6e1 $3e8b9507 $3e97a117 $3ea395c5 $3eaf713a $3ebb31a0 $3ec6d529 $3ed25a09 $3eddbe79 $3ee900b7 $3ef41f07 $3eff17b2 $3f04f484 $bea68f12 $be9aa086 $be8e9a22 $be827dc0 $be6c9a7f $be541501 $be3b6ecf $be22abb6 $be09cf86 $bde1bc2e $bdafb680 $bd7b2b74 $bd16c32c $bc490e90 $3c490e90 $3d16c32c $3d7b2b74 $3dafb680 $3de1bc2e $3e09cf86 $3e22abb6 $3e3b6ecf $3e541501 $3e6c9a7f $3e827dc0 $3e8e9a22 $3e9aa086 $3ea68f12 $3eb263ef $3ebe1d4a $3ec9b953 $3ed53641 $3ee0924f $3eebcbbb $3ef6e0cb $3f00e7e4 $3f064b82 $bea395c5 $be97a117 $be8b9507 $be7ee6e1 $be667c66 $be4dee60 $be354098 $be1c76de $be039502 $bdd53db9 $bda3308c $bd621469 $bcfb49ba $bbc90f88 $3c96c9b6 $3d2fe007 $3d8a200a $3dbc3ac3 $3dee3876 $3e1008b7 $3e28defc $3e419b37 $3e5a3997 $3e72b651 $3e8586ce $3e919ddd $3e9d9e78 $3ea986c4 $3eb554ec $3ec1071e $3ecc9b8b $3ed8106b $3ee363fa $3eee9479 $3ef9a02d $3f0242b1 $3f07a136
xr:$00000700= $a48d4000 xr:$00000704= $3cc90ab0 xr:$00000708= $3d48fb30 xr:$0000070c= $3d96a905 xr:$00000710= $3dc8bd36 xr:$00000714= $3dfab273 xr:$00000718= $3e164083 xr:$0000071c= $3e2f10a2 xr:$00000720= $3e47c5c2 xr:$00000724= $3e605c13 xr:$00000728= $3e78cfcc xr:$0000072c= $3e888e93 xr:$00000730= $3e94a031 xr:$00000734= $3ea09ae5 xr:$00000738= $3eac7cd4 xr:$0000073c= $3eb8442a xr:$00000740= $3ec3ef15 xr:$00000744= $3ecf7bca xr:$00000748= $3edae880 xr:$0000074c= $3ee63375 xr:$00000750= $3ef15aea xr:$00000754= $3efc5d27 xr:$00000758= $3f039c3d
B-6
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$0000075c= $3f08f59b xr:$00000760= $3f0e39da xr:$00000764= $3f13682a xr:$00000768= $3f187fc0 xr:$0000076c= $3f1d7fd1 xr:$00000770= $3f226799 xr:$00000774= $3f273656 xr:$00000778= $3f2beb4a xr:$0000077c= $3f3085bb xr:$00000780= $3f3504f3 xr:$00000784= $3f396842 xr:$00000788= $3f3daef9 xr:$0000078c= $3f41d870 xr:$00000790= $3f45e403 xr:$00000794= $3f49d112 xr:$00000798= $3f4d9f02 xr:$0000079c= $3f514d3d xr:$000007a0= $3f54db31 xr:$000007a4= $3f584853 xr:$000007a8= $3f5b941a xr:$000007ac= $3f5ebe05 xr:$000007b0= $3f61c598 xr:$000007b4= $3f64aa59 xr:$000007b8= $3f676bd8 xr:$000007bc= $3f6a09a7 xr:$000007c0= $3f6c835e xr:$000007c4= $3f6ed89e xr:$000007c8= $3f710908 xr:$000007cc= $3f731447 xr:$000007d0= $3f74fa0b xr:$000007d4= $3f76ba07 xr:$000007d8= $3f7853f8 xr:$000007dc= $3f79c79d xr:$000007e0= $3f7b14be xr:$000007e4= $3f7c3b28 xr:$000007e8= $3f7d3aac xr:$000007ec= $3f7e1324 $3f0a48ad $3f0f8784 $3f14b039 $3f19c200 $3f1ebc12 $3f239da9 $3f286605 $3f2d1469 $3f31a81d $3f36206c $3f3a7ca4 $3f3ebc1b $3f42de29 $3f46e22a $3f4ac77f $3f4e8d90 $3f5233c6 $3f55b993 $3f591e6a $3f5c61c7 $3f5f8327 $3f628210 $3f655e0b $3f6816a8 $3f6aab7b $3f6d1c1d $3f6f6830 $3f718f57 $3f73913f $3f756d97 $3f772417 $3f78b47b $3f7a1e84 $3f7b61fc $3f7c7eb0 $3f7d7474 $3f7e4323 $3f0b9a6b $3f10d3cd $3f15f6d9 $3f1b02c6 $3f1ff6cb $3f24d225 $3f299415 $3f2e3bde $3f32c8c9 $3f373a23 $3f3b8f3b $3f3fc767 $3f43e200 $3f47de65 $3f4bbbf8 $3f4f7a1f $3f531849 $3f5695e5 $3f59f26a $3f5d2d53 $3f604621 $3f633c5a $3f660f88 $3f68bf3c $3f6b4b0c $3f6db293 $3f6ff573 $3f721352 $3f740bdd $3f75dec6 $3f778bc5 $3f791298 $3f7a7302 $3f7baccd $3f7cbfc9 $3f7dabcc $3f7e70b0 $3f0cead0 $3f121eb0 $3f173c07 $3f1c420c $3f212ff9 $3f26050a $3f2ac082 $3f2f61a5 $3f33e7bc $3f385216 $3f3ca003 $3f40d0da $3f44e3f5 $3f48d8b3 $3f4cae79 $3f5064af $3f53fac3 $3f577026 $3f5ac450 $3f5df6be $3f6106f2 $3f63f473 $3f66becc $3f696591 $3f6be858 $3f6e46be $3f708066 $3f7294f8 $3f748422 $3f764d97 $3f77f110 $3f796e4e $3f7ac516 $3f7bf531 $3f7cfe73 $3f7de0b1 $3f7e9bc9
MOTOROLA
DSP96002/D, Rev. 2
B-7
X and Y Memory ROM Tables
Table B-1 X Memory ROM Contents (full cycle of cosine values) (Continued)
xr:$000007f0= xr:$000007f4= xr:$000007f8= xr:$000007fc= $3f7ec46d $3f7f4e6d $3f7fb10f $3f7fec43 $3f7eea9d $3f7f6ac7 $3f7fc38f $3f7ff4e6 $3f7f0e58 $3f7f84ab $3f7fd397 $3f7ffb11 $3f7f2f9d $3f7f9c18 $3f7fe129 $3f7ffec4
Table B-2 Y Memory ROM Contents (full cycle of sine values)
yr:$00000400= $00000000 yr:$00000404= $3cc90ab0 yr:$00000408= $3d48fb30 yr:$0000040c= $3d96a905 yr:$00000410= $3dc8bd36 yr:$00000414= $3dfab273 yr:$00000418= $3e164083 yr:$0000041c= $3e2f10a2 yr:$00000420= $3e47c5c2 yr:$00000424= $3e605c13 yr:$00000428= $3e78cfcc yr:$0000042c= $3e888e93 yr:$00000430= $3e94a031 yr:$00000434= $3ea09ae5 yr:$00000438= $3eac7cd4 yr:$0000043c= $3eb8442a yr:$00000440= $3ec3ef15 yr:$00000444= $3ecf7bca yr:$00000448= $3edae880 yr:$0000044c= $3ee63375 yr:$00000450= $3ef15aea yr:$00000454= $3efc5d27 yr:$00000458= $3f039c3d yr:$0000045c= $3f08f59b yr:$00000460= $3f0e39da yr:$00000464= $3f13682a yr:$00000468= $3f187fc0 yr:$0000046c= $3f1d7fd1 yr:$00000470= $3f226799 yr:$00000474= $3f273656 $3bc90f88 $3cfb49ba $3d621469 $3da3308c $3dd53db9 $3e039502 $3e1c76de $3e354098 $3e4dee60 $3e667c66 $3e7ee6e1 $3e8b9507 $3e97a117 $3ea395c5 $3eaf713a $3ebb31a0 $3ec6d529 $3ed25a09 $3eddbe79 $3ee900b7 $3ef41f07 $3eff17b2 $3f04f484 $3f0a48ad $3f0f8784 $3f14b039 $3f19c200 $3f1ebc12 $3f239da9 $3f286605 $3c490e90 $3d16c32c $3d7b2b74 $3dafb680 $3de1bc2e $3e09cf86 $3e22abb6 $3e3b6ecf $3e541501 $3e6c9a7f $3e827dc0 $3e8e9a22 $3e9aa086 $3ea68f12 $3eb263ef $3ebe1d4a $3ec9b953 $3ed53641 $3ee0924f $3eebcbbb $3ef6e0cb $3f00e7e4 $3f064b82 $3f0b9a6b $3f10d3cd $3f15f6d9 $3f1b02c6 $3f1ff6cb $3f24d225 $3f299415 $3c96c9b6 $3d2fe007 $3d8a200a $3dbc3ac3 $3dee3876 $3e1008b7 $3e28defc $3e419b37 $3e5a3997 $3e72b651 $3e8586ce $3e919ddd $3e9d9e78 $3ea986c4 $3eb554ec $3ec1071e $3ecc9b8b $3ed8106b $3ee363fa $3eee9479 $3ef9a02d $3f0242b1 $3f07a136 $3f0cead0 $3f121eb0 $3f173c07 $3f1c420c $3f212ff9 $3f26050a $3f2ac082
B-8
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$00000478= $3f2beb4a yr:$0000047c= $3f3085bb yr:$00000480= $3f3504f3 yr:$00000484= $3f396842 yr:$00000488= $3f3daef9 yr:$0000048c= $3f41d870 yr:$00000490= $3f45e403 yr:$00000494= $3f49d112 yr:$00000498= $3f4d9f02 yr:$0000049c= $3f514d3d yr:$000004a0= $3f54db31 yr:$000004a4= $3f584853 yr:$000004a8= $3f5b941a yr:$000004ac= $3f5ebe05 yr:$000004b0= $3f61c598 yr:$000004b4= $3f64aa59 yr:$000004b8= $3f676bd8 yr:$000004bc= $3f6a09a7 yr:$000004c0= $3f6c835e yr:$000004c4= $3f6ed89e yr:$000004c8= $3f710908 yr:$000004cc= $3f731447 yr:$000004d0= $3f74fa0b yr:$000004d4= $3f76ba07 yr:$000004d8= $3f7853f8 yr:$000004dc= $3f79c79d yr:$000004e0= $3f7b14be yr:$000004e4= $3f7c3b28 yr:$000004e8= $3f7d3aac yr:$000004ec= $3f7e1324 yr:$000004f0= yr:$000004f4= yr:$000004f8= yr:$000004fc= $3f7ec46d $3f7f4e6d $3f7fb10f $3f7fec43 $3f2d1469 $3f31a81d $3f36206c $3f3a7ca4 $3f3ebc1b $3f42de29 $3f46e22a $3f4ac77f $3f4e8d90 $3f5233c6 $3f55b993 $3f591e6a $3f5c61c7 $3f5f8327 $3f628210 $3f655e0b $3f6816a8 $3f6aab7b $3f6d1c1d $3f6f6830 $3f718f57 $3f73913f $3f756d97 $3f772417 $3f78b47b $3f7a1e84 $3f7b61fc $3f7c7eb0 $3f7d7474 $3f7e4323 $3f7eea9d $3f7f6ac7 $3f7fc38f $3f7ff4e6 $3f7ffec4 $3f7fe129 $3f7f9c18 $3f2e3bde $3f32c8c9 $3f373a23 $3f3b8f3b $3f3fc767 $3f43e200 $3f47de65 $3f4bbbf8 $3f4f7a1f $3f531849 $3f5695e5 $3f59f26a $3f5d2d53 $3f604621 $3f633c5a $3f660f88 $3f68bf3c $3f6b4b0c $3f6db293 $3f6ff573 $3f721352 $3f740bdd $3f75dec6 $3f778bc5 $3f791298 $3f7a7302 $3f7baccd $3f7cbfc9 $3f7dabcc $3f7e70b0 $3f7f0e58 $3f7f84ab $3f7fd397 $3f7ffb11 $3f7ffb11 $3f7fd397 $3f7f84ab $3f2f61a5 $3f33e7bc $3f385216 $3f3ca003 $3f40d0da $3f44e3f5 $3f48d8b3 $3f4cae79 $3f5064af $3f53fac3 $3f577026 $3f5ac450 $3f5df6be $3f6106f2 $3f63f473 $3f66becc $3f696591 $3f6be858 $3f6e46be $3f708066 $3f7294f8 $3f748422 $3f764d97 $3f77f110 $3f796e4e $3f7ac516 $3f7bf531 $3f7cfe73 $3f7de0b1 $3f7e9bc9 $3f7f2f9d $3f7f9c18 $3f7fe129 $3f7ffec4 $3f7ff4e6 $3f7fc38f $3f7f6ac7
yr:$00000500= $3f800000 yr:$00000504= $3f7fec43 yr:$00000508= $3f7fb10f
MOTOROLA
DSP96002/D, Rev. 2
B-9
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$0000050c= $3f7f4e6d yr:$00000510= $3f7ec46d yr:$00000514= $3f7e1324 yr:$00000518= $3f7d3aac yr:$0000051c= $3f7c3b28 yr:$00000520= $3f7b14be yr:$00000524= $3f79c79d yr:$00000528= $3f7853f8 yr:$0000052c= $3f76ba07 yr:$00000530= $3f74fa0b yr:$00000534= $3f731447 yr:$00000538= $3f710908 yr:$0000053c= $3f6ed89e yr:$00000540= $3f6c835e yr:$00000544= $3f6a09a7 yr:$00000548= $3f676bd8 yr:$0000054c= $3f64aa59 yr:$00000550= $3f61c598 yr:$00000554= $3f5ebe05 yr:$00000558= $3f5b941a yr:$0000055c= $3f584853 yr:$00000560= $3f54db31 yr:$00000564= $3f514d3d yr:$00000568= $3f4d9f02 yr:$0000056c= $3f49d112 yr:$00000570= $3f45e403 yr:$00000574= $3f41d870 yr:$00000578= $3f3daef9 yr:$0000057c= $3f396842 yr:$00000580= $3f3504f3 yr:$00000584= $3f3085bb yr:$00000588= $3f2beb4a yr:$0000058c= $3f273656 yr:$00000590= $3f226799 yr:$00000594= $3f1d7fd1 yr:$00000598= $3f187fc0 yr:$0000059c= $3f13682a $3f7f2f9d $3f7e9bc9 $3f7de0b1 $3f7cfe73 $3f7bf531 $3f7ac516 $3f796e4e $3f77f110 $3f764d97 $3f748422 $3f7294f8 $3f708066 $3f6e46be $3f6be858 $3f696591 $3f66becc $3f63f473 $3f6106f2 $3f5df6be $3f5ac450 $3f577026 $3f53fac3 $3f5064af $3f4cae79 $3f48d8b3 $3f44e3f5 $3f40d0da $3f3ca003 $3f385216 $3f33e7bc $3f2f61a5 $3f2ac082 $3f26050a $3f212ff9 $3f1c420c $3f173c07 $3f121eb0 $3f7f0e58 $3f7e70b0 $3f7dabcc $3f7cbfc9 $3f7baccd $3f7a7302 $3f791298 $3f778bc5 $3f75dec6 $3f740bdd $3f721352 $3f6ff573 $3f6db293 $3f6b4b0c $3f68bf3c $3f660f88 $3f633c5a $3f604621 $3f5d2d53 $3f59f26a $3f5695e5 $3f531849 $3f4f7a1f $3f4bbbf8 $3f47de65 $3f43e200 $3f3fc767 $3f3b8f3b $3f373a23 $3f32c8c9 $3f2e3bde $3f299415 $3f24d225 $3f1ff6cb $3f1b02c6 $3f15f6d9 $3f10d3cd $3f7eea9d $3f7e4323 $3f7d7474 $3f7c7eb0 $3f7b61fc $3f7a1e84 $3f78b47b $3f772417 $3f756d97 $3f73913f $3f718f57 $3f6f6830 $3f6d1c1d $3f6aab7b $3f6816a8 $3f655e0b $3f628210 $3f5f8327 $3f5c61c7 $3f591e6a $3f55b993 $3f5233c6 $3f4e8d90 $3f4ac77f $3f46e22a $3f42de29 $3f3ebc1b $3f3a7ca4 $3f36206c $3f31a81d $3f2d1469 $3f286605 $3f239da9 $3f1ebc12 $3f19c200 $3f14b039 $3f0f8784
B-10
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$000005a0= $3f0e39da yr:$000005a4= $3f08f59b yr:$000005a8= $3f039c3d yr:$000005ac= $3efc5d27 yr:$000005b0= $3ef15aea yr:$000005b4= $3ee63375 yr:$000005b8= $3edae880 yr:$000005bc= $3ecf7bca yr:$000005c0= $3ec3ef15 yr:$000005c4= $3eb8442a yr:$000005c8= $3eac7cd4 yr:$000005cc= $3ea09ae5 yr:$000005d0= $3e94a031 yr:$000005d4= $3e888e93 yr:$000005d8= $3e78cfcc yr:$000005dc= $3e605c13 yr:$000005e0= $3e47c5c2 yr:$000005e4= $3e2f10a2 yr:$000005e8= $3e164083 yr:$000005ec= $3dfab273 yr:$000005f0= yr:$000005f4= yr:$000005f8= yr:$000005fc= $3dc8bd36 $3d96a905 $3d48fb30 $3cc90ab0 $3f0cead0 $3f07a136 $3f0242b1 $3ef9a02d $3eee9479 $3ee363fa $3ed8106b $3ecc9b8b $3ec1071e $3eb554ec $3ea986c4 $3e9d9e78 $3e919ddd $3e8586ce $3e72b651 $3e5a3997 $3e419b37 $3e28defc $3e1008b7 $3dee3876 $3dbc3ac3 $3d8a200a $3d2fe007 $3c96c9b6 $bbc90f88 $bcfb49ba $bd621469 $bda3308c $bdd53db9 $be039502 $be1c76de $be354098 $be4dee60 $be667c66 $be7ee6e1 $be8b9507 $be97a117 $3f0b9a6b $3f064b82 $3f00e7e4 $3ef6e0cb $3eebcbbb $3ee0924f $3ed53641 $3ec9b953 $3ebe1d4a $3eb263ef $3ea68f12 $3e9aa086 $3e8e9a22 $3e827dc0 $3e6c9a7f $3e541501 $3e3b6ecf $3e22abb6 $3e09cf86 $3de1bc2e $3dafb680 $3d7b2b74 $3d16c32c $3c490e90 $bc490e90 $bd16c32c $bd7b2b74 $bdafb680 $bde1bc2e $be09cf86 $be22abb6 $be3b6ecf $be541501 $be6c9a7f $be827dc0 $be8e9a22 $be9aa086 $3f0a48ad $3f04f484 $3eff17b2 $3ef41f07 $3ee900b7 $3eddbe79 $3ed25a09 $3ec6d529 $3ebb31a0 $3eaf713a $3ea395c5 $3e97a117 $3e8b9507 $3e7ee6e1 $3e667c66 $3e4dee60 $3e354098 $3e1c76de $3e039502 $3dd53db9 $3da3308c $3d621469 $3cfb49ba $3bc90f88 $bc96c9b6 $bd2fe007 $bd8a200a $bdbc3ac3 $bdee3876 $be1008b7 $be28defc $be419b37 $be5a3997 $be72b651 $be8586ce $be919ddd $be9d9e78
yr:$00000600= $80000000 yr:$00000604= $bcc90ab0 yr:$00000608= $bd48fb30 yr:$0000060c= $bd96a905 yr:$00000610= $bdc8bd36 yr:$00000614= $bdfab273 yr:$00000618= $be164083 yr:$0000061c= $be2f10a2 yr:$00000620= $be47c5c2 yr:$00000624= $be605c13 yr:$00000628= $be78cfcc yr:$0000062c= $be888e93 yr:$00000630= $be94a031
MOTOROLA
DSP96002/D, Rev. 2
B-11
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$00000634= $bea09ae5 yr:$00000638= $beac7cd4 yr:$0000063c= $beb8442a yr:$00000640= $bec3ef15 yr:$00000644= $becf7bca yr:$00000648= $bedae880 yr:$0000064c= $bee63375 yr:$00000650= $bef15aea yr:$00000654= $befc5d27 yr:$00000658= $bf039c3d yr:$0000065c= $bf08f59b yr:$00000660= $bf0e39da yr:$00000664= $bf13682a yr:$00000668= $bf187fc0 yr:$0000066c= $bf1d7fd1 yr:$00000670= $bf226799 yr:$00000674= $bf273656 yr:$00000678= $bf2beb4a yr:$0000067c= $bf3085bb yr:$00000680= $bf3504f3 yr:$00000684= $bf396842 yr:$00000688= $bf3daef9 yr:$0000068c= $bf41d870 yr:$00000690= $bf45e403 yr:$00000694= $bf49d112 yr:$00000698= $bf4d9f02 yr:$0000069c= $bf514d3d yr:$000006a0= $bf54db31 yr:$000006a4= $bf584853 yr:$000006a8= $bf5b941a yr:$000006ac= $bf5ebe05 yr:$000006b0= $bf61c598 yr:$000006b4= $bf64aa59 yr:$000006b8= $bf676bd8 yr:$000006bc= $bf6a09a7 yr:$000006c0= $bf6c835e yr:$000006c4= $bf6ed89e $bea395c5 $beaf713a $bebb31a0 $bec6d529 $bed25a09 $beddbe79 $bee900b7 $bef41f07 $beff17b2 $bf04f484 $bf0a48ad $bf0f8784 $bf14b039 $bf19c200 $bf1ebc12 $bf239da9 $bf286605 $bf2d1469 $bf31a81d $bf36206c $bf3a7ca4 $bf3ebc1b $bf42de29 $bf46e22a $bf4ac77f $bf4e8d90 $bf5233c6 $bf55b993 $bf591e6a $bf5c61c7 $bf5f8327 $bf628210 $bf655e0b $bf6816a8 $bf6aab7b $bf6d1c1d $bf6f6830 $bea68f12 $beb263ef $bebe1d4a $bec9b953 $bed53641 $bee0924f $beebcbbb $bef6e0cb $bf00e7e4 $bf064b82 $bf0b9a6b $bf10d3cd $bf15f6d9 $bf1b02c6 $bf1ff6cb $bf24d225 $bf299415 $bf2e3bde $bf32c8c9 $bf373a23 $bf3b8f3b $bf3fc767 $bf43e200 $bf47de65 $bf4bbbf8 $bf4f7a1f $bf531849 $bf5695e5 $bf59f26a $bf5d2d53 $bf604621 $bf633c5a $bf660f88 $bf68bf3c $bf6b4b0c $bf6db293 $bf6ff573 $bea986c4 $beb554ec $bec1071e $becc9b8b $bed8106b $bee363fa $beee9479 $bef9a02d $bf0242b1 $bf07a136 $bf0cead0 $bf121eb0 $bf173c07 $bf1c420c $bf212ff9 $bf26050a $bf2ac082 $bf2f61a5 $bf33e7bc $bf385216 $bf3ca003 $bf40d0da $bf44e3f5 $bf48d8b3 $bf4cae79 $bf5064af $bf53fac3 $bf577026 $bf5ac450 $bf5df6be $bf6106f2 $bf63f473 $bf66becc $bf696591 $bf6be858 $bf6e46be $bf708066
B-12
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$000006c8= $bf710908 yr:$000006cc= $bf731447 yr:$000006d0= $bf74fa0b yr:$000006d4= $bf76ba07 yr:$000006d8= $bf7853f8 yr:$000006dc= $bf79c79d yr:$000006e0= $bf7b14be yr:$000006e4= $bf7c3b28 yr:$000006e8= $bf7d3aac yr:$000006ec= $bf7e1324 yr:$000006f0= yr:$000006f4= yr:$000006f8= yr:$000006fc= $bf7ec46d $bf7f4e6d $bf7fb10f $bf7fec43 $bf718f57 $bf73913f $bf756d97 $bf772417 $bf78b47b $bf7a1e84 $bf7b61fc $bf7c7eb0 $bf7d7474 $bf7e4323 $bf7eea9d $bf7f6ac7 $bf7fc38f $bf7ff4e6 $bf7ffec4 $bf7fe129 $bf7f9c18 $bf7f2f9d $bf7e9bc9 $bf7de0b1 $bf7cfe73 $bf7bf531 $bf7ac516 $bf796e4e $bf77f110 $bf764d97 $bf748422 $bf7294f8 $bf708066 $bf6e46be $bf6be858 $bf696591 $bf66becc $bf63f473 $bf6106f2 $bf5df6be $bf5ac450 $bf721352 $bf740bdd $bf75dec6 $bf778bc5 $bf791298 $bf7a7302 $bf7baccd $bf7cbfc9 $bf7dabcc $bf7e70b0 $bf7f0e58 $bf7f84ab $bf7fd397 $bf7ffb11 $bf7ffb11 $bf7fd397 $bf7f84ab $bf7f0e58 $bf7e70b0 $bf7dabcc $bf7cbfc9 $bf7baccd $bf7a7302 $bf791298 $bf778bc5 $bf75dec6 $bf740bdd $bf721352 $bf6ff573 $bf6db293 $bf6b4b0c $bf68bf3c $bf660f88 $bf633c5a $bf604621 $bf5d2d53 $bf59f26a $bf7294f8 $bf748422 $bf764d97 $bf77f110 $bf796e4e $bf7ac516 $bf7bf531 $bf7cfe73 $bf7de0b1 $bf7e9bc9 $bf7f2f9d $bf7f9c18 $bf7fe129 $bf7ffec4 $bf7ff4e6 $bf7fc38f $bf7f6ac7 $bf7eea9d $bf7e4323 $bf7d7474 $bf7c7eb0 $bf7b61fc $bf7a1e84 $bf78b47b $bf772417 $bf756d97 $bf73913f $bf718f57 $bf6f6830 $bf6d1c1d $bf6aab7b $bf6816a8 $bf655e0b $bf628210 $bf5f8327 $bf5c61c7 $bf591e6a
yr:$00000700= $bf800000 yr:$00000704= $bf7fec43 yr:$00000708= $bf7fb10f yr:$0000070c= $bf7f4e6d yr:$00000710= $bf7ec46d yr:$00000714= $bf7e1324 yr:$00000718= $bf7d3aac yr:$0000071c= $bf7c3b28 yr:$00000720= $bf7b14be yr:$00000724= $bf79c79d yr:$00000728= $bf7853f8 yr:$0000072c= $bf76ba07 yr:$00000730= $bf74fa0b yr:$00000734= $bf731447 yr:$00000738= $bf710908 yr:$0000073c= $bf6ed89e yr:$00000740= $bf6c835e yr:$00000744= $bf6a09a7 yr:$00000748= $bf676bd8 yr:$0000074c= $bf64aa59 yr:$00000750= $bf61c598 yr:$00000754= $bf5ebe05 yr:$00000758= $bf5b941a
MOTOROLA
DSP96002/D, Rev. 2
B-13
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$0000075c= $bf584853 yr:$00000760= $bf54db31 yr:$00000764= $bf514d3d yr:$00000768= $bf4d9f02 yr:$0000076c= $bf49d112 yr:$00000770= $bf45e403 yr:$00000774= $bf41d870 yr:$00000778= $bf3daef9 yr:$0000077c= $bf396842 yr:$00000780= $bf3504f3 yr:$00000784= $bf3085bb yr:$00000788= $bf2beb4a yr:$0000078c= $bf273656 yr:$00000790= $bf226799 yr:$00000794= $bf1d7fd1 yr:$00000798= $bf187fc0 yr:$0000079c= $bf13682a yr:$000007a0= $bf0e39da yr:$000007a4= $bf08f59b yr:$000007a8= $bf039c3d yr:$000007ac= $befc5d27 yr:$000007b0= $bef15aea yr:$000007b4= $bee63375 yr:$000007b8= $bedae880 yr:$000007bc= $becf7bca yr:$000007c0= $bec3ef15 yr:$000007c4= $beb8442a yr:$000007c8= $beac7cd4 yr:$000007cc= $bea09ae5 yr:$000007d0= $be94a031 yr:$000007d4= $be888e93 yr:$000007d8= $be78cfcc yr:$000007dc= $be605c13 yr:$000007e0= $be47c5c2 yr:$000007e4= $be2f10a2 yr:$000007e8= $be164083 yr:$000007ec= $bdfab273 $bf577026 $bf53fac3 $bf5064af $bf4cae79 $bf48d8b3 $bf44e3f5 $bf40d0da $bf3ca003 $bf385216 $bf33e7bc $bf2f61a5 $bf2ac082 $bf26050a $bf212ff9 $bf1c420c $bf173c07 $bf121eb0 $bf0cead0 $bf07a136 $bf0242b1 $bef9a02d $beee9479 $bee363fa $bed8106b $becc9b8b $bec1071e $beb554ec $bea986c4 $be9d9e78 $be919ddd $be8586ce $be72b651 $be5a3997 $be419b37 $be28defc $be1008b7 $bdee3876 $bf5695e5 $bf531849 $bf4f7a1f $bf4bbbf8 $bf47de65 $bf43e200 $bf3fc767 $bf3b8f3b $bf373a23 $bf32c8c9 $bf2e3bde $bf299415 $bf24d225 $bf1ff6cb $bf1b02c6 $bf15f6d9 $bf10d3cd $bf0b9a6b $bf064b82 $bf00e7e4 $bef6e0cb $beebcbbb $bee0924f $bed53641 $bec9b953 $bebe1d4a $beb263ef $bea68f12 $be9aa086 $be8e9a22 $be827dc0 $be6c9a7f $be541501 $be3b6ecf $be22abb6 $be09cf86 $bde1bc2e $bf55b993 $bf5233c6 $bf4e8d90 $bf4ac77f $bf46e22a $bf42de29 $bf3ebc1b $bf3a7ca4 $bf36206c $bf31a81d $bf2d1469 $bf286605 $bf239da9 $bf1ebc12 $bf19c200 $bf14b039 $bf0f8784 $bf0a48ad $bf04f484 $beff17b2 $bef41f07 $bee900b7 $beddbe79 $bed25a09 $bec6d529 $bebb31a0 $beaf713a $bea395c5 $be97a117 $be8b9507 $be7ee6e1 $be667c66 $be4dee60 $be354098 $be1c76de $be039502 $bdd53db9
B-14
DSP96002/D, Rev. 2
MOTOROLA
X and Y Memory ROM Tables
Table B-2 Y Memory ROM Contents (full cycle of sine values) (Continued)
yr:$000007f0= yr:$000007f4= yr:$000007f8= yr:$000007fc= $bdc8bd36 $bd96a905 $bd48fb30 $bcc90ab0 $bdbc3ac3 $bd8a200a $bd2fe007 $bc96c9b6 $bdafb680 $bd7b2b74 $bd16c32c $bc490e90 $bda3308c $bd621469 $bcfb49ba $bbc90f88
MOTOROLA
DSP96002/D, Rev. 2
B-15
X and Y Memory ROM Tables
B-16
DSP96002/D, Rev. 2
MOTOROLA
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